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John Crispin 4d6c4994fc ar71xx: Use PHY fixups for Open Mesh MR1750 ... The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in different ways. u-boot only modifies the ETH_CFG of the QCA955x based on the link speed. But OpenWrt can only modify the PHY delays based on the link speed. This can lead to communication problems when u-boot initializes the ETH_CFG for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY delays to an incompatible value. Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and only rely on the AT803x PHY settings. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49031		8 years ago
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arch/mips	ar71xx: Use PHY fixups for Open Mesh MR1750	8 years ago
drivers	ar71xx: reset ethernet tx ring on fast reset to prevent packet loss / irq issues	8 years ago
include/linux	ar71xx: add LED driver NU801	9 years ago
net/dsa	ar71xx: the ar7240 dsa driver is no longer used, remove it.	14 years ago