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550 lines
17 KiB
C
550 lines
17 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_fw_regs_common.h
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** PROJECT : UEIP
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** MODULES : ATM (ADSL)
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**
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** DATE : 1 AUG 2005
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM Driver (Firmware Register Structures)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 4 AUG 2005 Xu Liang Initiate Version
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** 23 OCT 2006 Xu Liang Add GPL header.
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** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
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*******************************************************************************/
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#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
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#define IFXMIPS_ATM_FW_REGS_COMMON_H
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#if defined(CONFIG_DANUBE)
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#include "ifxmips_atm_fw_regs_danube.h"
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#elif defined(CONFIG_AMAZON_SE)
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#include "ifxmips_atm_fw_regs_amazon_se.h"
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#elif defined(CONFIG_AR9)
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#include "ifxmips_atm_fw_regs_ar9.h"
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#elif defined(CONFIG_VR9)
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#include "ifxmips_atm_fw_regs_vr9.h"
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#else
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#error Platform is not specified!
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#endif
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/*
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* PPE ATM Cell Header
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*/
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#if defined(__BIG_ENDIAN)
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struct uni_cell_header {
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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};
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#else
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struct uni_cell_header {
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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};
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#endif // defined(__BIG_ENDIAN)
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/*
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* Inband Header and Trailer
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*/
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#if defined(__BIG_ENDIAN)
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struct rx_inband_trailer {
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/* 0 - 3h */
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unsigned int uu :8;
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unsigned int cpi :8;
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unsigned int stw_res1:4;
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unsigned int stw_clp :1;
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unsigned int stw_ec :1;
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unsigned int stw_uu :1;
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unsigned int stw_cpi :1;
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unsigned int stw_ovz :1;
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unsigned int stw_mfl :1;
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unsigned int stw_usz :1;
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unsigned int stw_crc :1;
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unsigned int stw_il :1;
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unsigned int stw_ra :1;
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unsigned int stw_res2:2;
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/* 4 - 7h */
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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};
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struct tx_inband_header {
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/* 0 - 3h */
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unsigned int gfc :4;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int clp :1;
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/* 4 - 7h */
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unsigned int uu :8;
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unsigned int cpi :8;
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unsigned int pad :8;
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unsigned int res1 :8;
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};
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#else
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struct rx_inband_trailer {
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/* 0 - 3h */
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unsigned int stw_res2:2;
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unsigned int stw_ra :1;
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unsigned int stw_il :1;
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unsigned int stw_crc :1;
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unsigned int stw_usz :1;
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unsigned int stw_mfl :1;
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unsigned int stw_ovz :1;
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unsigned int stw_cpi :1;
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unsigned int stw_uu :1;
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unsigned int stw_ec :1;
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unsigned int stw_clp :1;
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unsigned int stw_res1:4;
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unsigned int cpi :8;
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unsigned int uu :8;
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/* 4 - 7h */
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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};
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struct tx_inband_header {
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/* 0 - 3h */
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unsigned int clp :1;
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unsigned int pti :3;
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unsigned int vci :16;
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unsigned int vpi :8;
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unsigned int gfc :4;
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/* 4 - 7h */
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unsigned int res1 :8;
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unsigned int pad :8;
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unsigned int cpi :8;
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unsigned int uu :8;
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};
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#endif // defined(__BIG_ENDIAN)
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/*
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* MIB Table Maintained by Firmware
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*/
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struct wan_mib_table {
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u32 res1;
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u32 wrx_drophtu_cell;
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u32 wrx_dropdes_pdu;
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u32 wrx_correct_pdu;
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u32 wrx_err_pdu;
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u32 wrx_dropdes_cell;
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u32 wrx_correct_cell;
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u32 wrx_err_cell;
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u32 wrx_total_byte;
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u32 res2;
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u32 wtx_total_pdu;
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u32 wtx_total_cell;
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u32 wtx_total_byte;
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};
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/*
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* Host-PPE Communication Data Structure
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*/
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#if defined(__BIG_ENDIAN)
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struct fw_ver_id {
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unsigned int family :4;
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unsigned int fwtype :4;
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unsigned int interface :4;
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unsigned int fwmode :4;
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unsigned int major :8;
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unsigned int minor :8;
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};
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struct wrx_queue_config {
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/* 0h */
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unsigned int res2 :27;
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unsigned int dmach :4;
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unsigned int errdp :1;
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/* 1h */
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unsigned int oversize :16;
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unsigned int undersize :16;
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/* 2h */
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unsigned int res1 :16;
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unsigned int mfs :16;
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/* 3h */
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unsigned int uumask :8;
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unsigned int cpimask :8;
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unsigned int uuexp :8;
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unsigned int cpiexp :8;
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};
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struct wrx_queue_context {
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/* 0h */
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unsigned int curr_len :16;
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unsigned int res0 :12;
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unsigned int mfs :1;
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unsigned int ec :1;
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unsigned int clp1 :1;
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unsigned int aal5dp :1;
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/* 1h */
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unsigned int intcrc;
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/* 2h, 3h */
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unsigned int curr_des0;
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unsigned int curr_des1;
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/* 4h - 0xE */
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unsigned int res1[11];
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unsigned int last_dword;
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};
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struct wtx_port_config {
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unsigned int res1 :27;
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unsigned int qid :4;
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unsigned int qsben :1;
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};
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struct wtx_queue_config {
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unsigned int res1 :16;
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unsigned int same_vc_qmap:8;
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unsigned int res2 :1;
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unsigned int sbid :1;
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unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
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unsigned int res3 :1;
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unsigned int qsben :1;
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};
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struct wrx_desc_context {
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unsigned int dmach_wrptr : 16;
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unsigned int dmach_rdptr : 16;
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unsigned int res0 : 16;
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unsigned int dmach_fcnt : 16;
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unsigned int res1 : 11;
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unsigned int desbuf_wrptr : 5;
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unsigned int res2 : 11;
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unsigned int desbuf_rdptr : 5;
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unsigned int res3 : 27;
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unsigned int desbuf_vcnt : 5;
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};
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struct wrx_dma_channel_config {
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/* 0h */
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unsigned int res1 :1;
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unsigned int mode :2;
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unsigned int rlcfg :1;
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unsigned int desba :28;
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/* 1h */
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unsigned int chrl :16;
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unsigned int clp1th :16;
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/* 2h */
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unsigned int deslen :16;
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unsigned int vlddes :16;
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};
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struct wtx_dma_channel_config {
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/* 0h */
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unsigned int res2 :1;
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unsigned int mode :2;
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unsigned int res3 :1;
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unsigned int desba :28;
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/* 1h */
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unsigned int res1 :32;
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/* 2h */
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unsigned int deslen :16;
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unsigned int vlddes :16;
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};
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struct htu_entry {
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unsigned int res1 :1;
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unsigned int clp :1;
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unsigned int pid :2;
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unsigned int vpi :8;
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unsigned int vci :16;
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unsigned int pti :3;
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unsigned int vld :1;
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};
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struct htu_mask {
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unsigned int set :1;
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unsigned int clp :1;
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unsigned int pid_mask :2;
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unsigned int vpi_mask :8;
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unsigned int vci_mask :16;
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unsigned int pti_mask :3;
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unsigned int clear :1;
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};
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struct htu_result {
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unsigned int res1 :12;
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unsigned int cellid :4;
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unsigned int res2 :5;
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unsigned int type :1;
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unsigned int ven :1;
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unsigned int res3 :5;
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unsigned int qid :4;
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};
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struct rx_descriptor {
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/* 0 - 3h */
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unsigned int own :1;
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unsigned int c :1;
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int res1 :3;
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unsigned int byteoff :2;
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unsigned int res2 :2;
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unsigned int id :4;
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unsigned int err :1;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int res3 :4;
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unsigned int dataptr :28;
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};
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struct tx_descriptor {
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/* 0 - 3h */
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unsigned int own :1;
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unsigned int c :1;
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int byteoff :5;
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unsigned int res1 :5;
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unsigned int iscell :1;
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unsigned int clp :1;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int res2 :4;
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unsigned int dataptr :28;
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};
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#else
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struct wrx_queue_config {
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/* 0h */
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unsigned int errdp :1;
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unsigned int dmach :4;
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unsigned int res2 :27;
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/* 1h */
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unsigned int undersize :16;
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unsigned int oversize :16;
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/* 2h */
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unsigned int mfs :16;
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unsigned int res1 :16;
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/* 3h */
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unsigned int cpiexp :8;
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unsigned int uuexp :8;
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unsigned int cpimask :8;
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unsigned int uumask :8;
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};
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struct wtx_port_config {
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unsigned int qsben :1;
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unsigned int qid :4;
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unsigned int res1 :27;
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};
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struct wtx_queue_config {
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unsigned int qsben :1;
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unsigned int res3 :1;
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unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
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unsigned int sbid :1;
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unsigned int res2 :1;
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unsigned int same_vc_qmap:8;
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unsigned int res1 :16;
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};
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struct wrx_dma_channel_config
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{
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/* 0h */
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unsigned int desba :28;
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unsigned int rlcfg :1;
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unsigned int mode :2;
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unsigned int res1 :1;
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/* 1h */
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unsigned int clp1th :16;
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unsigned int chrl :16;
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/* 2h */
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unsigned int vlddes :16;
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unsigned int deslen :16;
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};
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struct wtx_dma_channel_config {
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/* 0h */
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unsigned int desba :28;
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unsigned int res3 :1;
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unsigned int mode :2;
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unsigned int res2 :1;
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/* 1h */
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unsigned int res1 :32;
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/* 2h */
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unsigned int vlddes :16;
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unsigned int deslen :16;
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};
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struct rx_descriptor {
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/* 4 - 7h */
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unsigned int dataptr :28;
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unsigned int res3 :4;
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/* 0 - 3h */
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unsigned int datalen :16;
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unsigned int err :1;
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unsigned int id :4;
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unsigned int res2 :2;
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unsigned int byteoff :2;
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unsigned int res1 :3;
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unsigned int eop :1;
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unsigned int sop :1;
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unsigned int c :1;
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unsigned int own :1;
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};
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struct tx_descriptor {
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/* 4 - 7h */
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unsigned int dataptr :28;
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unsigned int res2 :4;
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/* 0 - 3h */
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unsigned int datalen :16;
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unsigned int clp :1;
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unsigned int iscell :1;
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unsigned int res1 :5;
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unsigned int byteoff :5;
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unsigned int eop :1;
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unsigned int sop :1;
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unsigned int c :1;
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unsigned int own :1;
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};
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#endif // defined(__BIG_ENDIAN)
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#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
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#if defined(__BIG_ENDIAN)
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struct Retx_adsl_ppe_intf {
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unsigned int res0_0 : 16;
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unsigned int dtu_sid : 8;
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unsigned int dtu_timestamp : 8;
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unsigned int res1_0 : 16;
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unsigned int local_time : 8;
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unsigned int res1_1 : 5;
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unsigned int is_last_cw : 1;
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unsigned int reinit_flag : 1;
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unsigned int is_bad_cw : 1;
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};
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struct Retx_adsl_ppe_intf_rec {
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unsigned int local_time : 8;
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unsigned int res1_1 : 5;
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unsigned int is_last_cw : 1;
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unsigned int reinit_flag : 1;
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unsigned int is_bad_cw : 1;
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unsigned int dtu_sid : 8;
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unsigned int dtu_timestamp : 8;
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};
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struct Retx_mode_cfg {
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unsigned int res0 :8;
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unsigned int invld_range :8; // used for rejecting the too late arrival of the retransmitted DTU
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unsigned int buff_size :8; // the total number of cells in playout buffer is 32 * buff_size
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unsigned int res1 :7;
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unsigned int retx_en :1;
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};
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struct Retx_Tsync_cfg {
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unsigned int fw_alpha :16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)
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unsigned int sync_inp :16; // reserved
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};
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struct Retx_Td_cfg {
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unsigned int res0 :8;
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unsigned int td_max :8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
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unsigned int res1 :8;
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unsigned int td_min :8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
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};
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struct Retx_MIB_Timer_cfg {
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unsigned int ticks_per_sec : 16;
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unsigned int tick_cycle : 16;
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};
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struct DTU_stat_info {
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unsigned int complete : 1;
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unsigned int bad : 1;
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unsigned int res0_0 : 14;
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unsigned int time_stamp : 8;
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unsigned int cell_cnt : 8;
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unsigned int dtu_rd_ptr : 16;
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unsigned int dtu_wr_ptr : 16;
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};
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struct Retx_ctrl_field {
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unsigned int res0 : 1;
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unsigned int l2_drop : 1;
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unsigned int res1 : 13;
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unsigned int retx : 1;
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unsigned int dtu_sid : 8;
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unsigned int cell_sid : 8;
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};
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#else
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#error Little Endian is not supported yet.
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#endif
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struct dsl_param {
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unsigned int update_flag; // 00
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unsigned int res0; // 04
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unsigned int MinDelayrt; // 08
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unsigned int MaxDelayrt; // 0C
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unsigned int res1; // 10
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unsigned int res2; // 14
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unsigned int RetxEnable; // 18
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unsigned int ServiceSpecificReTx; // 1C
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unsigned int res3; // 20
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unsigned int ReTxPVC; // 24
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unsigned int res4; // 28
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unsigned int res5; // 2C
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unsigned int res6; // 30
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unsigned int res7; // 34
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unsigned int res8; // 38
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unsigned int res9; // 3C
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unsigned int res10; // 40
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unsigned int res11; // 44
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unsigned int res12; // 48
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unsigned int res13; // 4C
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unsigned int RxDtuCorruptedCNT; // 50
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unsigned int RxRetxDtuUnCorrectedCNT;// 54
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unsigned int RxLastEFB; // 58
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unsigned int RxDtuCorrectedCNT; // 5C
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};
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#endif
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#endif // IFXMIPS_ATM_FW_REGS_COMMON_H
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