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1311 lines
35 KiB
Diff
1311 lines
35 KiB
Diff
--- a/arch/powerpc/boot/Makefile
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+++ b/arch/powerpc/boot/Makefile
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@@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
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cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
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cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
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fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
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- cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
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+ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c rb333.c \
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cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
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virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
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cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
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@@ -242,6 +242,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
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image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
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image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
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image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
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+image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
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+ dtbImage.rb333
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# Board ports in arch/powerpc/platform/85xx/Kconfig
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image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
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--- /dev/null
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+++ b/arch/powerpc/boot/dts/rb600.dts
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@@ -0,0 +1,283 @@
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+/*
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+ * RouterBOARD 600 series Device Tree Source
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+ *
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+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ model = "RB600";
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+ compatible = "MPC83xx";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ aliases {
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+ ethernet0 = &enet0;
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+ ethernet1 = &enet1;
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+ pci0 = &pci0;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
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+ linux,stdout-path = "/soc8343@e0000000/serial@4500";
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ PowerPC,8343E@0 {
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+ device_type = "cpu";
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+ reg = <0x0>;
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+ d-cache-line-size = <0x20>;
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+ i-cache-line-size = <0x20>;
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+ d-cache-size = <0x8000>;
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+ i-cache-size = <0x8000>;
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+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
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+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
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+ };
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+
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+ cf@f9200000 {
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+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
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+ interrupt-at-level = <0x0>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x16 0x8>;
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+ lbc_extra_divider = <0x1>;
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+ reg = <0xf9200000 0x200000>;
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+ device_type = "rb,cf";
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+ };
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+
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+ cf@f9000000 {
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+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
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+ interrupt-at-level = <0x0>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x14 0x8>;
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+ lbc_extra_divider = <0x1>;
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+ reg = <0xf9000000 0x200000>;
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+ device_type = "rb,cf";
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+ };
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+
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+ flash {
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+ reg = <0xff800000 0x20000>;
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+ };
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+
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+ nnand {
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+ reg = <0xf0000000 0x1000>;
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+ };
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+
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+ nand {
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+ ale = <&gpio 0x6>;
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+ cle = <&gpio 0x5>;
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+ nce = <&gpio 0x4>;
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+ rdy = <&gpio 0x3>;
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+ reg = <0xf8000000 0x1000>;
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+ device_type = "rb,nand";
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+ };
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+
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+ fancon {
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x17 0x8>;
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+ sense = <&gpio 0x7>;
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+ fan_on = <&gpio 0x9>;
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+ };
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+
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+ pci0: pci@e0008500 {
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+ device_type = "pci";
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+ compatible = "fsl,mpc8349-pci";
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+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
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+ bus-range = <0x0 0x0>;
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+ interrupt-map = <
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+ 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
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+ 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
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+ 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
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+ 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
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+ 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
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+ 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
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+ 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
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+ 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
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+ 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
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+ 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
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+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
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+ 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
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+ 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
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+ 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
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+ 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
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+ 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
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+ 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
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+ 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
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+ 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
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+ 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
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+ 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
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+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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+ interrupt-parent = <&ipic>;
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+ };
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+
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+ soc8343@e0000000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ device_type = "soc";
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+ compatible = "simple-bus";
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+ ranges = <0x0 0xe0000000 0x100000>;
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+ reg = <0xe0000000 0x200>;
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+ bus-frequency = <0x1>;
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+
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+ led {
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+ user_led = <0x400 0x8>;
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+ };
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+
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+ beeper {
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+ reg = <0x500 0x100>;
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+ };
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+
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+ gpio: gpio@0 {
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+ reg = <0xc08 0x4>;
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+ device-id = <0x0>;
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+ compatible = "gpio";
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+ device_type = "gpio";
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+ };
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+
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+ dma@82a8 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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+ reg = <0x82a8 4>;
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+ ranges = <0 0x8100 0x1a8>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ cell-index = <0>;
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+ dma-channel@0 {
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+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0 0x80>;
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+ cell-index = <0>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@80 {
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+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x80 0x80>;
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+ cell-index = <1>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@100 {
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+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x100 0x80>;
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+ cell-index = <2>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@180 {
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+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x180 0x28>;
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+ cell-index = <3>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ };
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+
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+ enet0: ethernet@25000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ cell-index = <0>;
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+ phy-handle = <&phy0>;
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+ tbi-handle = <&tbi0>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
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+ local-mac-address = [00 00 00 00 00 00];
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+ reg = <0x25000 0x1000>;
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+ ranges = <0x0 0x25000 0x1000>;
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+ compatible = "gianfar";
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+ model = "TSEC";
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+ device_type = "network";
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+
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+ mdio@520 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,gianfar-tbi";
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+ reg = <0x520 0x20>;
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+
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+ tbi0: tbi-phy@11 {
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+ reg = <0x11>;
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+ device_type = "tbi-phy";
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+ };
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+ };
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+ };
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+
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+ enet1: ethernet@24000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ cell-index = <1>;
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+ phy-handle = <&phy1>;
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+ tbi-handle = <&tbi1>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
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+ local-mac-address = [00 00 00 00 00 00];
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+ reg = <0x24000 0x1000>;
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+ ranges = <0x0 0x24000 0x1000>;
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+ compatible = "gianfar";
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+ model = "TSEC";
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+ device_type = "network";
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+
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+ mdio@520 {
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+ #size-cells = <0x0>;
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+ #address-cells = <0x1>;
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+ reg = <0x520 0x20>;
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+ compatible = "fsl,gianfar-mdio";
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+
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+ phy0: ethernet-phy@0 {
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+ device_type = "ethernet-phy";
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+ reg = <0x0>;
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+ };
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+
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+ phy1: ethernet-phy@1 {
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+ device_type = "ethernet-phy";
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+ reg = <0x1>;
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+ };
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+
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+ tbi1: tbi-phy@11 {
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+ reg = <0x11>;
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+ device_type = "tbi-phy";
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+ };
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+ };
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+ };
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+
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+ ipic: pic@700 {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <2>;
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+ reg = <0x700 0x100>;
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+ device_type = "ipic";
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+ };
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+
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+ serial@4500 {
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x9 0x8>;
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+ clock-frequency = <0xfe4f840>;
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+ reg = <0x4500 0x100>;
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+ compatible = "ns16550";
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+ device_type = "serial";
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+ };
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+
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+ wdt@200 {
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+ reg = <0x200 0x100>;
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+ compatible = "mpc83xx_wdt";
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+ device_type = "watchdog";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/powerpc/boot/rb600.c
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@@ -0,0 +1,70 @@
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+/*
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+ * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
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+ *
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+ * Author: Michael Guntsche <mike@it-loops.com>
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+ *
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+ * Copyright (c) 2009 Michael Guntsche
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
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+ * by the Free Software Foundation.
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+ */
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+
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+#include "ops.h"
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+#include "types.h"
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+#include "io.h"
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+#include "stdio.h"
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+#include <libfdt.h>
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+
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+BSS_STACK(4*1024);
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+
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+u64 memsize64;
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+const void *fw_dtb;
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+
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+static void rb600_fixups(void)
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+{
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+ const u32 *reg, *timebase, *clock;
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+ int node, size;
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+
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+ dt_fixup_memory(0, memsize64);
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+
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+ /* Set the MAC addresses. */
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+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
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+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
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+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
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+
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+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
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+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
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+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
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+
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+ /* Find the CPU timebase and clock frequencies. */
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+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
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+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
|
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+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
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+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
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+
|
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+}
|
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+
|
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+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
+ unsigned long r6, unsigned long r7)
|
|
+{
|
|
+ const u32 *reg;
|
|
+ int node, size;
|
|
+
|
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+ fw_dtb = (const void *)r3;
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+
|
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+ /* Find the memory range. */
|
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+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
|
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+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
|
|
+ memsize64 = reg[1];
|
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+
|
|
+ /* Now we have the memory size; initialize the heap. */
|
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+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
|
|
+
|
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+ /* Prepare the device tree and find the console. */
|
|
+ fdt_init(_dtb_start);
|
|
+ serial_console_init();
|
|
+
|
|
+ /* Remaining fixups... */
|
|
+ platform_ops.fixups = rb600_fixups;
|
|
+}
|
|
--- a/arch/powerpc/boot/wrapper
|
|
+++ b/arch/powerpc/boot/wrapper
|
|
@@ -215,7 +215,7 @@ ps3)
|
|
link_address=''
|
|
pie=
|
|
;;
|
|
-ep88xc|ep405|ep8248e)
|
|
+ep88xc|ep405|ep8248e|rb600|rb333)
|
|
platformo="$object/fixed-head.o $object/$platform.o"
|
|
binary=y
|
|
;;
|
|
--- a/arch/powerpc/platforms/83xx/Kconfig
|
|
+++ b/arch/powerpc/platforms/83xx/Kconfig
|
|
@@ -38,6 +38,15 @@ config MPC832x_RDB
|
|
help
|
|
This option enables support for the MPC8323 RDB board.
|
|
|
|
+config RB_PPC
|
|
+ bool "MikroTik RouterBOARD 333/600 series"
|
|
+ select DEFAULT_UIMAGE
|
|
+ select QUICC_ENGINE
|
|
+ select PPC_MPC832x
|
|
+ select PPC_MPC834x
|
|
+ help
|
|
+ This option enables support for MikroTik RouterBOARD 333/600 series boards.
|
|
+
|
|
config MPC834x_MDS
|
|
bool "Freescale MPC834x MDS"
|
|
select DEFAULT_UIMAGE
|
|
--- /dev/null
|
|
+++ b/arch/powerpc/boot/dts/rb333.dts
|
|
@@ -0,0 +1,432 @@
|
|
+
|
|
+/*
|
|
+ * RouterBOARD 333 series Device Tree Source
|
|
+ *
|
|
+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
|
|
+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ *
|
|
+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
|
|
+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
|
|
+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
|
|
+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
|
|
+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
|
|
+ *
|
|
+ */
|
|
+
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+/ {
|
|
+ model = "RB333";
|
|
+ compatible = "MPC83xx";
|
|
+ #size-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+
|
|
+
|
|
+ aliases {
|
|
+ ethernet0 = &enet0;
|
|
+ ethernet1 = &enet1;
|
|
+ ethernet2 = &enet2;
|
|
+ pci0 = &pci0;
|
|
+ };
|
|
+
|
|
+
|
|
+ chosen {
|
|
+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
|
|
+ // linux,platform = <0x8062>;
|
|
+ // linux,initrd = <0x488000 0x0>;
|
|
+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
|
|
+ // interrupt-controller = <&ipic>;
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ #cpus = <1>;
|
|
+ #size-cells = <0>;
|
|
+ #address-cells = <1>;
|
|
+
|
|
+ PowerPC,8323E@0 {
|
|
+ device_type = "cpu";
|
|
+ reg = <0x0>;
|
|
+ i-cache-size = <0x4000>;
|
|
+ d-cache-size = <0x4000>;
|
|
+ i-cache-line-size = <0x20>;
|
|
+ d-cache-line-size = <0x20>;
|
|
+ // clock-frequency = <0x13de3650>;
|
|
+ // timebase-frequency = <0x1fc9f08>;
|
|
+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
|
|
+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
|
|
+ 32-bit;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ memory {
|
|
+ device_type = "memory";
|
|
+ reg = <0x0 0x4000000>;
|
|
+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
|
|
+ };
|
|
+
|
|
+ flash {
|
|
+ reg = <0xfe000000 0x20000>;
|
|
+ };
|
|
+
|
|
+ nand {
|
|
+ ale = <&gpio2 0x3>;
|
|
+ cle = <&gpio2 0x2>;
|
|
+ nce = <&gpio2 0x1>;
|
|
+ rdy = <&gpio2 0x0>;
|
|
+ reg = <0xf8000000 0x1000>;
|
|
+ device_type = "rb,nand";
|
|
+ };
|
|
+
|
|
+ nnand {
|
|
+ reg = <0xf0000000 0x1000>;
|
|
+ };
|
|
+
|
|
+ voltage {
|
|
+ voltage_gpio = <&gpio3 0x11>;
|
|
+ };
|
|
+
|
|
+ fancon {
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <0x14 0x8>;
|
|
+ fan_on = <&gpio0 0x10>;
|
|
+ };
|
|
+
|
|
+ pci0: pci@e0008500 {
|
|
+ device_type = "pci";
|
|
+ // compatible = "83xx";
|
|
+ compatible = "fsl,mpc8349-pci";
|
|
+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ // clock-frequency = <0>;
|
|
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
|
|
+ bus-range = <0x0 0x0>;
|
|
+ interrupt-map = <
|
|
+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
|
|
+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
|
|
+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
|
|
+
|
|
+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
|
|
+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
|
|
+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
|
|
+
|
|
+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
|
|
+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
|
|
+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
|
|
+
|
|
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ // interrupts = <66 0x8>;
|
|
+ };
|
|
+
|
|
+
|
|
+ qe@e0100000 {
|
|
+ reg = <0xe0100000 0x480>;
|
|
+ ranges = <0x0 0xe0100000 0x100000>;
|
|
+ model = "QE";
|
|
+ device_type = "qe";
|
|
+ compatible = "fsl,qe";
|
|
+ #size-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+ brg-frequency = <0>;
|
|
+ bus-frequency = <0>;
|
|
+ // bus-frequency = <198000000>;
|
|
+ fsl,qe-num-riscs = <1>;
|
|
+ fsl,qe-num-snums = <28>;
|
|
+
|
|
+ qeic: qeic@80 {
|
|
+ interrupt-controller;
|
|
+ compatible = "fsl,qe-ic";
|
|
+ big-endian;
|
|
+ built-in;
|
|
+ reg = <0x80 0x80>;
|
|
+ #interrupt-cells = <1>;
|
|
+ #address-cells = <0>;
|
|
+ device_type = "qeic";
|
|
+ interrupts = <0x20 0x8 0x21 0x8>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ };
|
|
+
|
|
+ mdio@2120 {
|
|
+ compatible = "ucc_geth_phy";
|
|
+ device_type = "mdio";
|
|
+ reg = <0x3120 0x18>;
|
|
+ #size-cells = <0>;
|
|
+ #address-cells = <1>;
|
|
+
|
|
+ phy3: ethernet-phy@03 {
|
|
+ // interface = <0x3>;
|
|
+ device_type = "ethernet-phy";
|
|
+ reg = <0x3>;
|
|
+ };
|
|
+
|
|
+ phy2: ethernet-phy@02 {
|
|
+ // interface = <0x3>;
|
|
+ device_type = "ethernet-phy";
|
|
+ reg = <0x2>;
|
|
+ };
|
|
+
|
|
+ phy1: ethernet-phy@01 {
|
|
+ // interface = <0x3>;
|
|
+ device_type = "ethernet-phy";
|
|
+ reg = <0x1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ enet0: ucc@2200 {
|
|
+ tx-clock = <0x1a>;
|
|
+ rx-clock = <0x1f>;
|
|
+ mac-address = [00 0c 42 1c 29 d2];
|
|
+ interrupt-parent = <&qeic>;
|
|
+ interrupts = <0x22>;
|
|
+ reg = <0x2200 0x200>;
|
|
+ device-id = <0x3>;
|
|
+ model = "UCC";
|
|
+ compatible = "ucc_geth";
|
|
+ device_type = "network";
|
|
+ phy-handle = <&phy2>;
|
|
+ pio-handle = <&pio3>;
|
|
+ };
|
|
+
|
|
+ enet1: ucc@3200 {
|
|
+ tx-clock = <0x22>;
|
|
+ rx-clock = <0x20>;
|
|
+ mac-address = [00 0c 42 1c 29 d1];
|
|
+ interrupt-parent = <&qeic>;
|
|
+ interrupts = <0x23>;
|
|
+ reg = <0x3200 0x200>;
|
|
+ device-id = <0x4>;
|
|
+ model = "UCC";
|
|
+ compatible = "ucc_geth";
|
|
+ device_type = "network";
|
|
+ phy-handle = <&phy3>;
|
|
+ pio-handle = <&pio4>;
|
|
+ };
|
|
+
|
|
+ enet2: ucc@3000 {
|
|
+ tx-clock = <0x18>;
|
|
+ rx-clock = <0x17>;
|
|
+ mac-address = [00 0c 42 1c 29 d0];
|
|
+ interrupt-parent = <&qeic>;
|
|
+ interrupts = <0x21>;
|
|
+ reg = <0x3000 0x200>;
|
|
+ device-id = <0x2>;
|
|
+ model = "UCC";
|
|
+ compatible = "ucc_geth";
|
|
+ device_type = "network";
|
|
+ phy-handle = <&phy1>;
|
|
+ pio-handle = <&pio2>;
|
|
+ };
|
|
+
|
|
+ spi@500 {
|
|
+ mode = "cpu";
|
|
+ interrupt-parent = <&qeic>;
|
|
+ interrupts = <0x1>;
|
|
+ reg = <0x500 0x40>;
|
|
+ compatible = "fsl,spi";
|
|
+ device_type = "spi";
|
|
+ };
|
|
+
|
|
+ spi@4c0 {
|
|
+ mode = "cpu";
|
|
+ interrupt-parent = <&qeic>;
|
|
+ interrupts = <0x2>;
|
|
+ reg = <0x4c0 0x40>;
|
|
+ compatible = "fsl,spi";
|
|
+ device_type = "spi";
|
|
+ };
|
|
+
|
|
+ muram@10000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
|
+ ranges = <0x0 0x10000 0x4000>;
|
|
+ device_type = "muram";
|
|
+
|
|
+ data-only@0 {
|
|
+ compatible = "fsl,qe-muram-data",
|
|
+ "fsl,cpm-muram-data";
|
|
+ reg = <0x0 0x4000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
+ soc8323@e0000000 {
|
|
+ bus-frequency = <0x1>;
|
|
+ reg = <0xe0000000 0x200>;
|
|
+ ranges = <0x0 0xe0000000 0x100000>;
|
|
+ device_type = "soc";
|
|
+ compatible = "simple-bus";
|
|
+ #interrupt-cells = <0x2>;
|
|
+ #size-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+
|
|
+ beeper {
|
|
+ gpio = <&gpio3 0x12>;
|
|
+ reg = <0x500 0x100>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <0x48 0x8>;
|
|
+ };
|
|
+
|
|
+ gpio3: gpio@3 {
|
|
+ reg = <0x144c 0x4>;
|
|
+ device-id = <0x3>;
|
|
+ compatible = "qe_gpio";
|
|
+ device_type = "gpio";
|
|
+ };
|
|
+
|
|
+ gpio2: gpio@2 {
|
|
+ reg = <0x1434 0x4>;
|
|
+ device-id = <0x2>;
|
|
+ compatible = "qe_gpio";
|
|
+ device_type = "gpio";
|
|
+ };
|
|
+
|
|
+ gpio0: gpio@0 {
|
|
+ reg = <0x1404 0x4>;
|
|
+ device-id = <0x0>;
|
|
+ compatible = "qe_gpio";
|
|
+ device_type = "gpio";
|
|
+ };
|
|
+
|
|
+ par_io@1400 {
|
|
+ num-ports = <4>;
|
|
+ device_type = "par_io";
|
|
+ reg = <0x1400 0x100>;
|
|
+
|
|
+ pio4: ucc_pin@04 {
|
|
+ pio-map = <
|
|
+ /* port pin dir open_drain assignment has_irq */
|
|
+ 1 18 1 0 1 0
|
|
+ 1 19 1 0 1 0
|
|
+ 1 20 1 0 1 0
|
|
+ 1 21 1 0 1 0
|
|
+ 1 30 1 0 1 0
|
|
+ 3 20 2 0 1 0
|
|
+ 1 30 2 0 1 0
|
|
+ 1 31 2 0 1 0
|
|
+ 1 22 2 0 1 0
|
|
+ 1 23 2 0 1 0
|
|
+ 1 24 2 0 1 0
|
|
+ 1 25 2 0 1 0
|
|
+ 1 28 2 0 1 0
|
|
+ 1 26 2 0 1 0
|
|
+ 3 21 2 0 1 0>;
|
|
+ };
|
|
+
|
|
+ pio3: ucc_pin@03 {
|
|
+ pio-map = <
|
|
+ /* port pin dir open_drain assignment has_irq */
|
|
+ 1 0 1 0 1 0
|
|
+ 1 1 1 0 1 0
|
|
+ 1 2 1 0 1 0
|
|
+ 1 3 1 0 1 0
|
|
+ 1 12 1 0 1 0
|
|
+ 3 24 2 0 1 0
|
|
+ 1 11 2 0 1 0
|
|
+ 1 13 2 0 1 0
|
|
+ 1 4 2 0 1 0
|
|
+ 1 5 2 0 1 0
|
|
+ 1 6 2 0 1 0
|
|
+ 1 7 2 0 1 0
|
|
+ 1 10 2 0 1 0
|
|
+ 1 8 2 0 1 0
|
|
+ 3 29 2 0 1 0>;
|
|
+ };
|
|
+
|
|
+ pio2: ucc_pin@02 {
|
|
+ pio-map = <
|
|
+ /* port pin dir open_drain assignment has_irq */
|
|
+ 3 4 3 0 2 0
|
|
+ 3 5 1 0 2 0
|
|
+ 0 18 1 0 1 0
|
|
+ 0 19 1 0 1 0
|
|
+ 0 20 1 0 1 0
|
|
+ 0 21 1 0 1 0
|
|
+ 0 30 1 0 1 0
|
|
+ 3 6 2 0 1 0
|
|
+ 0 29 2 0 1 0
|
|
+ 0 31 2 0 1 0
|
|
+ 0 22 2 0 1 0
|
|
+ 0 23 2 0 1 0
|
|
+ 0 24 2 0 1 0
|
|
+ 0 25 2 0 1 0
|
|
+ 0 28 2 0 1 0
|
|
+ 0 26 2 0 1 0
|
|
+ 3 31 2 0 1 0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ipic: pic@700 {
|
|
+ device_type = "ipic";
|
|
+ built-in;
|
|
+ reg = <0x700 0x100>;
|
|
+ #interrupt-cells = <0x2>;
|
|
+ #address-cells = <0x0>;
|
|
+ interrupt-controller;
|
|
+ };
|
|
+
|
|
+
|
|
+ serial@4500 {
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <0x9 0x8>;
|
|
+ clock-frequency = <0x7f27c20>;
|
|
+ reg = <0x4500 0x100>;
|
|
+ compatible = "ns16550";
|
|
+ device_type = "serial";
|
|
+ };
|
|
+
|
|
+ dma@82a8 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
|
|
+ reg = <0x82a8 4>;
|
|
+ ranges = <0 0x8100 0x1a8>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <71 8>;
|
|
+ cell-index = <0>;
|
|
+ dma-channel@0 {
|
|
+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
+ reg = <0 0x80>;
|
|
+ cell-index = <0>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <71 8>;
|
|
+ };
|
|
+ dma-channel@80 {
|
|
+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
+ reg = <0x80 0x80>;
|
|
+ cell-index = <1>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <71 8>;
|
|
+ };
|
|
+ dma-channel@100 {
|
|
+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
+ reg = <0x100 0x80>;
|
|
+ cell-index = <2>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <71 8>;
|
|
+ };
|
|
+ dma-channel@180 {
|
|
+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
|
|
+ reg = <0x180 0x28>;
|
|
+ cell-index = <3>;
|
|
+ interrupt-parent = <&ipic>;
|
|
+ interrupts = <71 8>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wdt@200 {
|
|
+ reg = <0x200 0x100>;
|
|
+ compatible = "mpc83xx_wdt";
|
|
+ device_type = "watchdog";
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/powerpc/boot/rb333.c
|
|
@@ -0,0 +1,73 @@
|
|
+/*
|
|
+ * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
|
|
+ *
|
|
+ * Author: Alexandros C. Couloumbis <alex@ozo.com>
|
|
+ * Author: Michael Guntsche <mike@it-loops.com>
|
|
+ *
|
|
+ * Copyright (c) 2010 Alexandros C. Couloumbis
|
|
+ * Copyright (c) 2009 Michael Guntsche
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ */
|
|
+
|
|
+#include "ops.h"
|
|
+#include "types.h"
|
|
+#include "io.h"
|
|
+#include "stdio.h"
|
|
+#include <libfdt.h>
|
|
+
|
|
+BSS_STACK(4*1024);
|
|
+
|
|
+u64 memsize64;
|
|
+const void *fw_dtb;
|
|
+
|
|
+static void rb333_fixups(void)
|
|
+{
|
|
+ const u32 *timebase, *clock;
|
|
+ int node, size;
|
|
+ void *chosen;
|
|
+ const char* bootargs;
|
|
+
|
|
+ dt_fixup_memory(0, memsize64);
|
|
+
|
|
+ /* Find the CPU timebase and clock frequencies. */
|
|
+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
|
|
+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
|
|
+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
|
|
+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
|
|
+
|
|
+ /* Fixup chosen
|
|
+ * The bootloader reads the kernelparm segment and adds the content to
|
|
+ * bootargs. This is needed to specify root and other boot flags.
|
|
+ */
|
|
+ chosen = finddevice("/chosen");
|
|
+ node = fdt_path_offset(fw_dtb, "/chosen");
|
|
+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
|
|
+ setprop_str(chosen, "bootargs", bootargs);
|
|
+}
|
|
+
|
|
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
+ unsigned long r6, unsigned long r7)
|
|
+{
|
|
+ const u32 *reg;
|
|
+ int node, size;
|
|
+
|
|
+ fw_dtb = (const void *)r3;
|
|
+
|
|
+ /* Find the memory range. */
|
|
+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
|
|
+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
|
|
+ memsize64 = reg[1];
|
|
+
|
|
+ /* Now we have the memory size; initialize the heap. */
|
|
+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
|
|
+
|
|
+ /* Prepare the device tree and find the console. */
|
|
+ fdt_init(_dtb_start);
|
|
+ serial_console_init();
|
|
+
|
|
+ /* Remaining fixups... */
|
|
+ platform_ops.fixups = rb333_fixups;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/arch/powerpc/platforms/83xx/rbppc.c
|
|
@@ -0,0 +1,388 @@
|
|
+/*
|
|
+ * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
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+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
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+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
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+ * Copyright (C) Mikrotik 2007
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#include <linux/delay.h>
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+#include <linux/root_dev.h>
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+#include <linux/initrd.h>
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+#include <linux/interrupt.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_device.h>
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+#include <linux/of_platform.h>
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+#include <linux/pci.h>
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+#include <asm/time.h>
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+#include <asm/ipic.h>
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+#include <asm/udbg.h>
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+#include <asm/qe.h>
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+#include <asm/qe_ic.h>
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+#include <sysdev/fsl_soc.h>
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+#include <sysdev/fsl_pci.h>
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+#include "mpc83xx.h"
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+
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+#define SYSCTL 0x100
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+#define SICRL 0x014
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+
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+#define GTCFR2 0x04
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+#define GTMDR4 0x22
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+#define GTRFR4 0x26
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+#define GTCNR4 0x2e
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+#define GTVER4 0x36
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+#define GTPSR4 0x3e
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+
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+#define GTCFR_BCM 0x40
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+#define GTCFR_STP4 0x20
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+#define GTCFR_RST4 0x10
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+#define GTCFR_STP3 0x02
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+#define GTCFR_RST3 0x01
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+
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+#define GTMDR_ORI 0x10
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+#define GTMDR_FRR 0x08
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+#define GTMDR_ICLK16 0x04
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+
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+extern int par_io_data_set(u8 port, u8 pin, u8 val);
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+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
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+ int assignment, int has_irq);
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+
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+static unsigned timer_freq;
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+static void *gtm;
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+
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+static int beeper_irq;
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+static unsigned beeper_gpio_pin[2];
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+
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+int rb333model = 0;
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+
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+irqreturn_t rbppc_timer_irq(int irq, void *ptr)
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+{
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+ static int toggle = 0;
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+
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+ par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
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+ toggle = !toggle;
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+
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+ /* ack interrupt */
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+ out_be16(gtm + GTVER4, 3);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+void rbppc_beep(unsigned freq)
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+{
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+ unsigned gtmdr;
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+
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+ if (freq > 5000) freq = 5000;
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+
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+ if (!gtm)
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+ return;
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+ if (!freq) {
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+ out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
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+ return;
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+ }
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+
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+ out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
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+ out_be16(gtm + GTPSR4, 255);
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+ gtmdr = GTMDR_FRR | GTMDR_ICLK16;
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+ if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
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+ out_be16(gtm + GTMDR4, gtmdr);
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+ out_be16(gtm + GTVER4, 3);
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+
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+ out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
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+ out_be16(gtm + GTCNR4, 0);
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+}
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+EXPORT_SYMBOL(rbppc_beep);
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+
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+static void __init rbppc_setup_arch(void)
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+{
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+ struct device_node *np;
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+
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+ np = of_find_node_by_type(NULL, "cpu");
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+ if (np) {
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+ const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
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+ loops_per_jiffy = fp ? *fp / HZ : 0;
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+
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+ of_node_put(np);
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+ }
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+
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+ np = of_find_node_by_name(NULL, "serial");
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+ if (np) {
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+ timer_freq =
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+ *(unsigned *) of_get_property(np, "clock-frequency", NULL);
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+ of_node_put(np);
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+ }
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+
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+#ifdef CONFIG_PCI
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+ np = of_find_node_by_type(NULL, "pci");
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+ if (np) {
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+ mpc83xx_add_bridge(np);
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+ }
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+#endif
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+
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+if (rb333model) {
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+
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+#ifdef CONFIG_QUICC_ENGINE
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+ qe_reset();
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+
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+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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+ par_io_init(np);
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+ of_node_put(np);
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+
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+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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+ par_io_of_config(np);
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+ }
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+#endif
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+
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+} /* RB333 */
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+
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+}
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+
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+void __init rbppc_init_IRQ(void)
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+{
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+ struct device_node *np;
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+
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+ np = of_find_node_by_type(NULL, "ipic");
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+ if (np) {
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+ ipic_init(np, 0);
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+ ipic_set_default_priority();
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+ of_node_put(np);
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+ }
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+
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+if (rb333model) {
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+
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+#ifdef CONFIG_QUICC_ENGINE
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+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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+ if (!np) {
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+ np = of_find_node_by_type(NULL, "qeic");
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+ if (!np)
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+ return;
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+ }
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+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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+ of_node_put(np);
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+#endif /* CONFIG_QUICC_ENGINE */
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+
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+} /* RB333 */
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+
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+}
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+
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+static int __init rbppc_probe(void)
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+{
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+ char *model;
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+
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+ model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
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+
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+ if (!model)
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+ return 0;
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+
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+ if (strcmp(model, "RB333") == 0) {
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+ rb333model = 1;
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+ return 1;
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+ }
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+
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+ if (strcmp(model, "RB600") == 0)
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+ return 1;
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+
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+ return 0;
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+}
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+
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+static void __init rbppc_beeper_init(struct device_node *beeper)
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+{
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+ struct resource res;
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+ struct device_node *gpio;
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+ const unsigned *pin;
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+ const unsigned *gpio_id;
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+
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+ if (of_address_to_resource(beeper, 0, &res)) {
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+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
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+ return;
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+ }
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+
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+ pin = of_get_property(beeper, "gpio", NULL);
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+ if (pin) {
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+ gpio = of_find_node_by_phandle(pin[0]);
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+
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+ if (!gpio) {
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+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
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+ return;
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+ }
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+
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+ gpio_id = of_get_property(gpio, "device-id", NULL);
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+ if (!gpio_id) {
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+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
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+ return;
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+ }
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+
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+ beeper_gpio_pin[0] = *gpio_id;
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+ beeper_gpio_pin[1] = pin[1];
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+
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+ par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
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+ } else {
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+ void *sysctl;
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+
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+ sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
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+ out_be32(sysctl + SICRL,
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+ in_be32(sysctl + SICRL) | (1 << (31 - 19)));
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+ iounmap(sysctl);
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+ }
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+
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+ gtm = ioremap_nocache(res.start, res.end - res.start + 1);
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+
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+ beeper_irq = irq_of_parse_and_map(beeper, 0);
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+ if (beeper_irq != NO_IRQ) {
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+ int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
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+ if (e) {
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+ printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
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+ }
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+ }
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+}
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+
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+#define SBIT(x) (0x80000000 >> (x))
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+#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
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+
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+#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
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+#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
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+
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+#define SICRL_RB600(x) ((x) + (0x114 >> 2))
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+#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
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+#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
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+
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+static void rbppc_restart(char *cmd)
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+{
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+ __be32 __iomem *reg;
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+ unsigned rb_model;
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+ struct device_node *root;
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+ unsigned int size;
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+
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+ root = of_find_node_by_path("/");
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+ if (root) {
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+ const char *prop = (char *) of_get_property(root, "model", &size);
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+ rb_model = prop[sizeof("RB") - 1] - '0';
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+ of_node_put(root);
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+ switch (rb_model) {
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+ case 3:
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+ reg = ioremap(get_immrbase(), 0x2000);
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+ local_irq_disable();
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+ out_be32(GPIO_DIR_RB333(reg),
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+ (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
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+ out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
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+ break;
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+ case 6:
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+ reg = ioremap(get_immrbase(), 0x1000);
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+ local_irq_disable();
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+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
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+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
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+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
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+ break;
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+ default:
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+ mpc83xx_restart(cmd);
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+ break;
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+ }
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+ }
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+ else mpc83xx_restart(cmd);
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+
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+ for (;;) ;
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+}
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+
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+static void rbppc_halt(void)
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+{
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+ while (1);
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+}
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+
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+static struct of_device_id rbppc_ids[] = {
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+ { .type = "soc", },
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+ { .compatible = "soc", },
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+ { .compatible = "simple-bus", },
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+ { .type = "qe", },
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+ { .compatible = "fsl,qe", },
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+ { .compatible = "gianfar", },
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+ { },
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+};
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+
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+static int __init rbppc_declare_of_platform_devices(void)
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+{
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+ struct device_node *np;
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+ unsigned idx;
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+
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+ of_platform_bus_probe(NULL, rbppc_ids, NULL);
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+
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+ np = of_find_node_by_type(NULL, "mdio");
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+ if (np) {
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+ unsigned len;
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+ unsigned *res;
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+ const unsigned *eres;
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+ struct device_node *ep;
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+
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+ ep = of_find_compatible_node(NULL, "network", "ucc_geth");
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+ if (ep) {
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+ eres = of_get_property(ep, "reg", &len);
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+ res = (unsigned *) of_get_property(np, "reg", &len);
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+ if (res && eres) {
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+ res[0] = eres[0] + 0x120;
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+ }
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+ }
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+ }
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+
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+ np = of_find_node_by_name(NULL, "nand");
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+ if (np) {
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+ of_platform_device_create(np, "nand", NULL);
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+ }
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+
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+ idx = 0;
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+ for_each_node_by_type(np, "rb,cf") {
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+ char dev_name[12];
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+ snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
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+ of_platform_device_create(np, dev_name, NULL);
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+ ++idx;
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+ }
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+
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+ np = of_find_node_by_name(NULL, "beeper");
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+ if (np) {
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+ rbppc_beeper_init(np);
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+ }
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+
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+ return 0;
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+}
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+machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
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+
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+define_machine(rb600) {
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+ .name = "MikroTik RouterBOARD 333/600 series",
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+ .probe = rbppc_probe,
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+ .setup_arch = rbppc_setup_arch,
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+ .init_IRQ = rbppc_init_IRQ,
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+ .get_irq = ipic_get_irq,
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+ .restart = rbppc_restart,
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+ .halt = rbppc_halt,
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+ .time_init = mpc83xx_time_init,
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+ .calibrate_decr = generic_calibrate_decr,
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+};
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+
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+static void fixup_pcibridge(struct pci_dev *dev)
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+{
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+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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+ /* let the kernel itself set right memory windows */
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+ pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
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+ pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
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+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
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+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
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+ pci_write_config_byte(dev, PCI_IO_BASE, 0);
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+ pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
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+
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+ pci_write_config_byte(
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+ dev, PCI_COMMAND,
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+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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+ }
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+}
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+
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+
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+static void fixup_rb604(struct pci_dev *dev)
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+{
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+ pci_write_config_byte(dev, 0xC0, 0x01);
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+}
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+
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+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
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+DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
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