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69 lines
2.5 KiB
Diff
69 lines
2.5 KiB
Diff
From ff83e3023cb8fc3b5dfc12e0c91bf1eb9dc4c4c6 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Sat, 21 Mar 2020 14:36:24 +0100
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Subject: [PATCH] staging: mt7621-pci-phy: re-do 'xtal_mode' detection
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Detection of the Xtal mode is using magic numbers that
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can be avoided using properly some definitions and a more
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accurate variable name from 'reg' into 'xtal_mode'. This
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increase readability.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20200321133624.31388-4-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 15 ++++++++++-----
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1 file changed, 10 insertions(+), 5 deletions(-)
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--- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
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+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
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@@ -75,6 +75,9 @@
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#define RG_PE1_FRC_MSTCKDIV BIT(5)
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+#define XTAL_MODE_SEL_SHIFT 6
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+#define XTAL_MODE_SEL_MASK 0x7
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+
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#define MAX_PHYS 2
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/**
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@@ -136,9 +139,11 @@ static void mt7621_bypass_pipe_rst(struc
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static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
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{
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struct device *dev = phy->dev;
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- u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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+ u32 xtal_mode;
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+
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+ xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)
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+ >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
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- reg = (reg >> 6) & 0x7;
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/* Set PCIe Port PHY to disable SSC */
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/* Debug Xtal Type */
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mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
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@@ -154,13 +159,13 @@ static void mt7621_set_phy_for_ssc(struc
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RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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}
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- if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
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+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
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/* Set Pre-divider ratio (for host mode) */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_PREDIV,
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RG_PE1_H_PLL_PREDIV_VAL(0x01));
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dev_info(dev, "Xtal is 40MHz\n");
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- } else if (reg >= 6) { /* 25MHz Xal */
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+ } else if (xtal_mode >= 6) { /* 25MHz Xal */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_PREDIV,
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RG_PE1_H_PLL_PREDIV_VAL(0x00));
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@@ -206,7 +211,7 @@ static void mt7621_set_phy_for_ssc(struc
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
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RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
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- if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
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+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
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/* set force mode enable of da_pe1_mstckdiv */
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mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
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RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
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