You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
115 lines
2.7 KiB
Diff
115 lines
2.7 KiB
Diff
From bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b Mon Sep 17 00:00:00 2001
|
|
From: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Date: Wed, 25 Jul 2018 10:37:46 +0200
|
|
Subject: [PATCH] ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq
|
|
support
|
|
|
|
This adds some operating points for cpu frequeny scaling
|
|
|
|
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Signed-off-by: John Crispin <john@phrozen.org>
|
|
Signed-off-by: Andy Gross <andy.gross@linaro.org>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 58 ++++++++++++++---------------
|
|
1 file changed, 30 insertions(+), 28 deletions(-)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -59,14 +59,8 @@
|
|
reg = <0x0>;
|
|
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
|
clock-frequency = <0>;
|
|
- operating-points = <
|
|
- /* kHz uV (fixed) */
|
|
- 48000 1100000
|
|
- 200000 1100000
|
|
- 500000 1100000
|
|
- 716000 1100000
|
|
- >;
|
|
clock-latency = <256000>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@1 {
|
|
@@ -79,14 +73,8 @@
|
|
reg = <0x1>;
|
|
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
|
clock-frequency = <0>;
|
|
- operating-points = <
|
|
- /* kHz uV (fixed) */
|
|
- 48000 1100000
|
|
- 200000 1100000
|
|
- 500000 1100000
|
|
- 666000 1100000
|
|
- >;
|
|
clock-latency = <256000>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@2 {
|
|
@@ -99,14 +87,8 @@
|
|
reg = <0x2>;
|
|
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
|
clock-frequency = <0>;
|
|
- operating-points = <
|
|
- /* kHz uV (fixed) */
|
|
- 48000 1100000
|
|
- 200000 1100000
|
|
- 500000 1100000
|
|
- 666000 1100000
|
|
- >;
|
|
clock-latency = <256000>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@3 {
|
|
@@ -119,14 +101,8 @@
|
|
reg = <0x3>;
|
|
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
|
clock-frequency = <0>;
|
|
- operating-points = <
|
|
- /* kHz uV (fixed) */
|
|
- 48000 1100000
|
|
- 200000 1100000
|
|
- 500000 1100000
|
|
- 666000 1100000
|
|
- >;
|
|
clock-latency = <256000>;
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
L2: l2-cache {
|
|
@@ -136,6 +112,32 @@
|
|
};
|
|
};
|
|
|
|
+ cpu0_opp_table: opp_table0 {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+
|
|
+ opp-48000000 {
|
|
+ opp-hz = /bits/ 64 <48000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ clock-latency-ns = <256000>;
|
|
+ };
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ clock-latency-ns = <256000>;
|
|
+ };
|
|
+ opp-500000000 {
|
|
+ opp-hz = /bits/ 64 <500000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ clock-latency-ns = <256000>;
|
|
+ };
|
|
+ opp-716000000 {
|
|
+ opp-hz = /bits/ 64 <716000000>;
|
|
+ opp-microvolt = <1100000>;
|
|
+ clock-latency-ns = <256000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
pmu {
|
|
compatible = "arm,cortex-a7-pmu";
|
|
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
|