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280 lines
5.7 KiB
Diff
280 lines
5.7 KiB
Diff
From fbc9fb0c2d30f2141e1b0b824f473276c3aef528 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Aug 2014 17:53:24 +0200
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Subject: [PATCH 24/57] MIPS: ralink: add mt7628an devicetree files
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/Kconfig | 4 +
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arch/mips/ralink/dts/Makefile | 1 +
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arch/mips/ralink/dts/mt7628an.dtsi | 184 ++++++++++++++++++++++++++++++++
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arch/mips/ralink/dts/mt7628an_eval.dts | 54 ++++++++++
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4 files changed, 243 insertions(+)
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create mode 100644 arch/mips/ralink/dts/mt7628an.dtsi
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create mode 100644 arch/mips/ralink/dts/mt7628an_eval.dts
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -75,6 +75,10 @@ choice
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bool "MT7620A eval kit"
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depends on SOC_MT7620
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+ config DTB_MT7628AN_EVAL
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+ bool "MT7620A eval kit"
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+ depends on SOC_MT7620
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+
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config DTB_MT7621_EVAL
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bool "MT7621 eval kit"
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depends on SOC_MT7621
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--- a/arch/mips/ralink/dts/Makefile
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+++ b/arch/mips/ralink/dts/Makefile
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@@ -3,3 +3,4 @@ obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_
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obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
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obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
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obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
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+obj-$(CONFIG_DTB_MT7628AN_EVAL) := mt7628an_eval.dtb.o
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7628an.dtsi
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@@ -0,0 +1,184 @@
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,mtk7628an-soc";
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+
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+ cpus {
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+ cpu@0 {
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+ compatible = "mips,mips24KEc";
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+ };
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+ };
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+
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+ cpuintc: cpuintc@0 {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ compatible = "mti,cpu-interrupt-controller";
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+ };
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+
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+ palmbus@10000000 {
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+ compatible = "palmbus";
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+ reg = <0x10000000 0x200000>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ sysc@0 {
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+ compatible = "ralink,mt7620a-sysc";
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+ reg = <0x0 0x100>;
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+ };
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+
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+ watchdog@120 {
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+ compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
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+ reg = <0x120 0x10>;
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+
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+ resets = <&rstctrl 8>;
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+ reset-names = "wdt";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <24>;
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+ };
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+
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+ intc: intc@200 {
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+ compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
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+ reg = <0x200 0x100>;
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+
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+ resets = <&rstctrl 9>;
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+ reset-names = "intc";
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <2>;
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+
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+ ralink,intc-registers = <0x9c 0xa0
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+ 0x6c 0xa4
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+ 0x80 0x78>;
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+ };
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+
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+ memc@300 {
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+ compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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+ reg = <0x300 0x100>;
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+
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+ resets = <&rstctrl 20>;
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+ reset-names = "mc";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <3>;
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+ };
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+
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+ gpio@600 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
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+ reg = <0x600 0x100>;
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+
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+ gpio0: bank@0 {
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+ reg = <0>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ gpio1: bank@1 {
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+ reg = <1>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ gpio2: bank@2 {
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+ reg = <2>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+ };
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+
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+ spi@b00 {
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+ compatible = "ralink,mt7621-spi";
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+ reg = <0xb00 0x100>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "spi";
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_pins>;
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+
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+ status = "disabled";
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+ };
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+
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+ uartlite@c00 {
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+ compatible = "ns16550a";
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+ reg = <0xc00 0x100>;
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+
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+ reg-shift = <2>;
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+ reg-io-width = <4>;
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+ no-loopback-test;
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+
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+ resets = <&rstctrl 12>;
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+ reset-names = "uartl";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <20>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ };
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+ };
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+
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+ pinctrl {
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+ compatible = "ralink,rt2880-pinmux";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&state_default>;
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+ state_default: pinctrl0 {
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+ };
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+ spi_pins: spi {
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+ spi {
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+ ralink,group = "spi";
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+ ralink,function = "spi";
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+ };
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+ };
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+ uart0_pins: uartlite {
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+ uart {
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+ ralink,group = "uart0";
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+ ralink,function = "uart";
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+ };
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+ };
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+ };
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+
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+ rstctrl: rstctrl {
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+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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+ #reset-cells = <1>;
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+ };
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+
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+ usbphy {
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+ compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
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+
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+ resets = <&rstctrl 22>;
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+ reset-names = "host";
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+ };
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+
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+ ehci@101c0000 {
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+ compatible = "ralink,rt3xxx-ehci";
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+ reg = <0x101c0000 0x1000>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <18>;
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+ };
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+
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+ ohci@101c1000 {
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+ compatible = "ralink,rt3xxx-ohci";
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+ reg = <0x101c1000 0x1000>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <18>;
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+ };
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+
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+};
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7628an_eval.dts
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@@ -0,0 +1,54 @@
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+/dts-v1/;
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+
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+/include/ "mt7628an.dtsi"
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+
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+/ {
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+ compatible = "ralink,mt7628an-eval-board", "ralink,mt7628an-soc";
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+ model = "Ralink MT7628AN evaluation board";
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+
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+ memory@0 {
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+ reg = <0x0 0x2000000>;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,57600 init=/init";
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+ };
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+
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+ palmbus@10000000 {
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+ spi@b00 {
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+ status = "okay";
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+
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+ m25p80@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "en25q64";
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+ reg = <0 0>;
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+ linux,modalias = "m25p80", "en25q64";
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+ spi-max-frequency = <10000000>;
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+
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+ partition@0 {
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+ label = "u-boot";
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+ reg = <0x0 0x30000>;
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+ read-only;
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+ };
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+
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+ partition@30000 {
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+ label = "u-boot-env";
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+ reg = <0x30000 0x10000>;
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+ read-only;
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+ };
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+
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+ factory: partition@40000 {
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+ label = "factory";
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+ reg = <0x40000 0x10000>;
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+ read-only;
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+ };
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+
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+ partition@50000 {
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+ label = "firmware";
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+ reg = <0x50000 0x7b0000>;
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+ };
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+ };
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+ };
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+ };
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+};
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