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111 lines
3.6 KiB
Diff
111 lines
3.6 KiB
Diff
From e93fc4ed811c7dcc6b0c93716f760431fc645ba2 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 26 Dec 2019 15:48:09 +0100
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Subject: [PATCH] drm/vc4: crtc: Move the cob allocation outside of
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bind
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The COB allocation depends on the HVS channel used for a given
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pixelvalve.
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While the channel allocation was entirely static in vc4, vc5 changes
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that and at bind time, a pixelvalve can be assigned to multiple
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HVS channels.
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Let's prepare that rework by allocating the COB when it's actually
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needed.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 39 +++++++++++++++++-----------------
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drivers/gpu/drm/vc4/vc4_drv.h | 2 --
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2 files changed, 20 insertions(+), 21 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -65,6 +65,23 @@ static const struct debugfs_reg32 crtc_r
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VC4_REG32(PV_HACT_ACT),
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};
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+static unsigned int
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+vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc, unsigned int channel)
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+{
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+ struct drm_device *drm = vc4_crtc->base.dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(drm);
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+
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+ u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
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+ /* Top/base are supposed to be 4-pixel aligned, but the
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+ * Raspberry Pi firmware fills the low bits (which are
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+ * presumably ignored).
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+ */
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+ u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
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+ u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
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+
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+ return top - base + 4;
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+}
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+
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bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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bool in_vblank_irq, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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@@ -73,6 +90,7 @@ bool vc4_crtc_get_scanoutpos(struct drm_
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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+ unsigned int cob_size;
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u32 val;
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int fifo_lines;
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int vblank_lines;
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@@ -108,8 +126,9 @@ bool vc4_crtc_get_scanoutpos(struct drm_
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*hpos += mode->crtc_htotal / 2;
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}
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+ cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc->channel);
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/* This is the offset we need for translating hvs -> pv scanout pos. */
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- fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
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+ fifo_lines = cob_size / mode->crtc_hdisplay;
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if (fifo_lines > 0)
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ret = true;
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@@ -1104,22 +1123,6 @@ static void vc4_set_crtc_possible_masks(
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}
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}
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-static void
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-vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
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-{
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- struct drm_device *drm = vc4_crtc->base.dev;
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- struct vc4_dev *vc4 = to_vc4_dev(drm);
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- u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
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- /* Top/base are supposed to be 4-pixel aligned, but the
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- * Raspberry Pi firmware fills the low bits (which are
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- * presumably ignored).
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- */
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- u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
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- u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
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-
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- vc4_crtc->cob_size = top - base + 4;
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-}
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-
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static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@@ -1174,8 +1177,6 @@ static int vc4_crtc_bind(struct device *
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*/
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drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
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- vc4_crtc_get_cob_allocation(vc4_crtc);
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-
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CRTC_WRITE(PV_INTEN, 0);
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -477,8 +477,6 @@ struct vc4_crtc {
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u8 lut_r[256];
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u8 lut_g[256];
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u8 lut_b[256];
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- /* Size in pixels of the COB memory allocated to this CRTC. */
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- u32 cob_size;
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struct drm_pending_vblank_event *event;
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