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158 lines
5.4 KiB
Diff
158 lines
5.4 KiB
Diff
From cda32ee78d8b448bcbfc8e3d55dc04d809657ce2 Mon Sep 17 00:00:00 2001
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From: Ran Wang <ran.wang_1@nxp.com>
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Date: Wed, 20 Nov 2019 14:09:23 +0800
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Subject: [PATCH] LF-387-4 usb: dwc3: Add cache type configuration support
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This feature is telling how to configure cache type on 4 different
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transfer types: Data Read, Desc Read, Data Write and Desc write. For each
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treasfer type, controller has a 4-bit register field to enable different
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cache type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
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----------------------------------------------------------------
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MBUS_TYPE| bit[3] |bit[2] |bit[1] |bit[0]
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----------------------------------------------------------------
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AHB |Cacheable |Bufferable |Privilegge |Data
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AXI3 |Write Allocate|Read Allocate|Cacheable |Bufferable
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AXI4 |Allocate Other|Allocate |Modifiable |Bufferable
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AXI4 |Other Allocate|Allocate |Modifiable |Bufferable
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Native |Same as AXI |Same as AXI |Same as AXI|Same as AXI
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----------------------------------------------------------------
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Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
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signals, which have the same meaning:
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Bufferable = Posted
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Cacheable = Modifiable = Snoop (negation of No Snoop)
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In most cases, driver support is not required unless the default values of
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registers are not correct *and* DWC3 node has enabled dma-coherent. So far we
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have observed USB device detect failure on some Layerscape platforms if this
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programming was not applied.
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Related struct:
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struct dwc3_cache_type {
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u8 transfer_type_datard;
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u8 transfer_type_descrd;
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u8 transfer_type_datawr;
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u8 transfer_type_descwr;
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};
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Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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Reviewed-by: Jun Li <jun.li@nxp.com>
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---
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drivers/usb/dwc3/core.c | 67 ++++++++++++++++++++++++++++++++++++++++++++-----
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drivers/usb/dwc3/core.h | 15 +++++++++++
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2 files changed, 76 insertions(+), 6 deletions(-)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -913,6 +913,53 @@ static void dwc3_set_power_down_clk_scal
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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+#ifdef CONFIG_OF
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+struct dwc3_cache_type {
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+ u8 transfer_type_datard;
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+ u8 transfer_type_descrd;
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+ u8 transfer_type_datawr;
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+ u8 transfer_type_descwr;
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+};
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+
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+static const struct dwc3_cache_type ls1088a_dwc3_cache_type = {
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+ .transfer_type_datard = 2,
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+ .transfer_type_descrd = 2,
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+ .transfer_type_datawr = 2,
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+ .transfer_type_descwr = 2,
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+};
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+
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+/**
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+ * dwc3_set_cache_type - Configure cache type registers
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+ * @dwc: Pointer to our controller context structure
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+ */
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+static void dwc3_set_cache_type(struct dwc3 *dwc)
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+{
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+ u32 tmp, reg;
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+ const struct dwc3_cache_type *cache_type =
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+ device_get_match_data(dwc->dev);
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+
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+ if (cache_type) {
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+ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
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+ tmp = reg;
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+
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+ reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
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+ reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
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+
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+ reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
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+ reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
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+
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+ reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
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+ reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
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+
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+ reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
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+ reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
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+
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+ if (tmp != reg)
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+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
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+ }
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+}
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+#endif
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+
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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@@ -973,6 +1020,10 @@ static int dwc3_core_init(struct dwc3 *d
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dwc3_set_incr_burst_type(dwc);
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+#ifdef CONFIG_OF
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+ dwc3_set_cache_type(dwc);
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+#endif
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+
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usb_phy_set_suspend(dwc->usb2_phy, 0);
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usb_phy_set_suspend(dwc->usb3_phy, 0);
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ret = phy_power_on(dwc->usb2_generic_phy);
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@@ -1895,12 +1946,16 @@ static const struct dev_pm_ops dwc3_dev_
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#ifdef CONFIG_OF
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static const struct of_device_id of_dwc3_match[] = {
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- {
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- .compatible = "snps,dwc3"
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- },
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- {
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- .compatible = "synopsys,dwc3"
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- },
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+ { .compatible = "fsl,ls1012a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls1021a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls1028a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls1043a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls1046a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls1088a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,ls2088a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "fsl,lx2160a-dwc3", .data = &ls1088a_dwc3_cache_type, },
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+ { .compatible = "snps,dwc3" },
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+ { .compatible = "synopsys,dwc3" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_match);
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -166,6 +166,21 @@
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/* Bit fields */
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/* Global SoC Bus Configuration INCRx Register 0 */
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+#ifdef CONFIG_OF
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+#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
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+#define DWC3_GSBUSCFG0_DATARD(n) (((n) & 0xf) \
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+ << DWC3_GSBUSCFG0_DATARD_SHIFT)
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+#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
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+#define DWC3_GSBUSCFG0_DESCRD(n) (((n) & 0xf) \
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+ << DWC3_GSBUSCFG0_DESCRD_SHIFT)
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+#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
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+#define DWC3_GSBUSCFG0_DATAWR(n) (((n) & 0xf) \
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+ << DWC3_GSBUSCFG0_DATAWR_SHIFT)
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+#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
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+#define DWC3_GSBUSCFG0_DESCWR(n) (((n) & 0xf) \
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+ << DWC3_GSBUSCFG0_DESCWR_SHIFT)
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+#endif
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+
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#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
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#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
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#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
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