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124 lines
3.6 KiB
Diff
124 lines
3.6 KiB
Diff
From d408e9c29dd580cb94e39da2b0eef81061d22061 Mon Sep 17 00:00:00 2001
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From: Ran Wang <ran.wang_1@nxp.com>
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Date: Thu, 19 Dec 2019 17:02:36 +0800
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Subject: [PATCH] LF-387-1 Revert "usb: dwc3: Add cache type configuration
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support"
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This reverts commit ebceaf435cc96892d22b334b2a6517374c0d6a6e.
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Will use next version patch to replace this.
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Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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---
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drivers/usb/dwc3/core.c | 61 +++++--------------------------------------------
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drivers/usb/dwc3/core.h | 15 ------------
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2 files changed, 6 insertions(+), 70 deletions(-)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -913,54 +913,6 @@ static void dwc3_set_power_down_clk_scal
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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-#ifdef CONFIG_OF
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-struct dwc3_cache_type {
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- u8 transfer_type_datard;
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- u8 transfer_type_descrd;
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- u8 transfer_type_datawr;
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- u8 transfer_type_descwr;
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-};
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-
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-static const struct dwc3_cache_type layerscape_dwc3_cache_type = {
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- .transfer_type_datard = 2,
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- .transfer_type_descrd = 2,
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- .transfer_type_datawr = 2,
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- .transfer_type_descwr = 2,
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-};
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-
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-/**
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- * dwc3_set_cache_type - Configure cache type registers
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- * @dwc: Pointer to our controller context structure
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- */
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-static void dwc3_set_cache_type(struct dwc3 *dwc)
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-{
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- u32 tmp, reg;
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- const struct dwc3_cache_type *cache_type =
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- device_get_match_data(dwc->dev);
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-
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- if (cache_type) {
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- reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
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- tmp = reg;
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-
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- reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
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- reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
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-
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- reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
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- reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
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-
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- reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
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- reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
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-
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- reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
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- reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
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-
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- if (tmp != reg)
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- dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
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- }
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-}
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-#endif
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-
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-
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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@@ -1021,10 +973,6 @@ static int dwc3_core_init(struct dwc3 *d
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dwc3_set_incr_burst_type(dwc);
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-#ifdef CONFIG_OF
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- dwc3_set_cache_type(dwc);
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-#endif
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-
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usb_phy_set_suspend(dwc->usb2_phy, 0);
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usb_phy_set_suspend(dwc->usb3_phy, 0);
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ret = phy_power_on(dwc->usb2_generic_phy);
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@@ -1947,9 +1895,12 @@ static const struct dev_pm_ops dwc3_dev_
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#ifdef CONFIG_OF
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static const struct of_device_id of_dwc3_match[] = {
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- { .compatible = "fsl,layerscape-dwc3", .data = &layerscape_dwc3_cache_type, },
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- { .compatible = "snps,dwc3" },
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- { .compatible = "synopsys,dwc3" },
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+ {
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+ .compatible = "snps,dwc3"
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+ },
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+ {
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+ .compatible = "synopsys,dwc3"
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+ },
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{ },
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_match);
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -166,21 +166,6 @@
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/* Bit fields */
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/* Global SoC Bus Configuration INCRx Register 0 */
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-#ifdef CONFIG_OF
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-#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
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-#define DWC3_GSBUSCFG0_DATARD(n) (((n) & 0xf) \
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- << DWC3_GSBUSCFG0_DATARD_SHIFT)
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-#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
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-#define DWC3_GSBUSCFG0_DESCRD(n) (((n) & 0xf) \
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- << DWC3_GSBUSCFG0_DESCRD_SHIFT)
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-#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
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-#define DWC3_GSBUSCFG0_DATAWR(n) (((n) & 0xf) \
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- << DWC3_GSBUSCFG0_DATAWR_SHIFT)
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-#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
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-#define DWC3_GSBUSCFG0_DESCWR(n) (((n) & 0xf) \
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- << DWC3_GSBUSCFG0_DESCWR_SHIFT)
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-#endif
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-
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#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
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#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
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#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
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