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74 lines
2.5 KiB
Diff
74 lines
2.5 KiB
Diff
From 5f1673ff67d5e8acf590fb5a4cc2d0d5d4115927 Mon Sep 17 00:00:00 2001
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Date: Tue, 6 Nov 2018 10:14:57 +0800
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Subject: [PATCH] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
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When LX2 PCIe controller is sending multiple split completions and
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ACK latency expires indicating that ACK should be send at priority.
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But because of large number of split completions and FC update DLLP,
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the controller does not give priority to ACK transmission. This
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results into ACK latency timer timeout error at the link partner and
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the pending TLPs are replayed by the link partner again.
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Workaround:
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1. Reduce the ACK latency timeout value to a very small value.
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2. Restrict the number of completions from the LX2 PCIe controller
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to 1, by changing the Max Read Request Size (MRRS) of link partner
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to the same value as Max Packet size (MPS).
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This patch implemented part 1, the part 2 can be set by kernel parameter
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'pci=pcie_bus_perf'
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This ERRATA is only for LX2160A Rev1.0, and it will be fixed
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in Rev2.0.
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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---
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drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 15 +++++++++++++++
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drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4 ++++
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2 files changed, 19 insertions(+)
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--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
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+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
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@@ -80,12 +80,27 @@ static bool ls_pcie_g4_is_bridge(struct
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return header_type == PCI_HEADER_TYPE_BRIDGE;
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}
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+static void workaround_A011451(struct ls_pcie_g4 *pcie)
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+{
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+ struct mobiveil_pcie *mv_pci = &pcie->pci;
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+ u32 val;
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+
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+ /* Set ACK latency timeout */
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+ val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
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+ val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
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+ val |= (4 << ACK_LAT_TO_VAL_SHIFT);
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+ csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
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+}
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+
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static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
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{
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struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
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pcie->rev = csr_readb(pci, PCI_REVISION_ID);
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+ if (pcie->rev == REV_1_0)
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+ workaround_A011451(pcie);
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+
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return 0;
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}
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--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
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+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
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@@ -86,6 +86,10 @@
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#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
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#define PAB_INTP_AXI_PIO_CLASS 0x474
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+#define GPEX_ACK_REPLAY_TO 0x438
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+#define ACK_LAT_TO_VAL_MASK 0x1fff
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+#define ACK_LAT_TO_VAL_SHIFT 0
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+
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#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
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#define AMAP_CTRL_EN_SHIFT 0
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#define AMAP_CTRL_TYPE_SHIFT 1
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