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35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 10208caf7f0ebfb3d6b546aa2ae66e42462551e0 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Wed, 4 Dec 2013 14:37:52 +0100
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Subject: [PATCH 164/203] ARM: mvebu: fix register length for Armada XP PMSU
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The per-CPU PMSU registers documented in the datasheet start at
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0x22100 and the last register for CPU3 is at 0x22428. However, the DT
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informations use <0x22100 0x430>, which makes the region end at
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0x22530 and not 0x22430.
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Moreover, looking at the datasheet, we can see that the registers for
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CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and
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for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have
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been used per CPU.
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Therefore, this commit reduces the length of the PMSU per-CPU register
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area from the incorrect 0x430 bytes to a more logical 0x400 bytes.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/boot/dts/armada-xp.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/boot/dts/armada-xp.dtsi
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+++ b/arch/arm/boot/dts/armada-xp.dtsi
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@@ -48,7 +48,7 @@
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armada-370-xp-pmsu@22000 {
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compatible = "marvell,armada-370-xp-pmsu";
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- reg = <0x22100 0x430>, <0x20800 0x20>;
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+ reg = <0x22100 0x400>, <0x20800 0x20>;
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};
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serial@12200 {
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