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139 lines
4.1 KiB
Diff
139 lines
4.1 KiB
Diff
From b5289e9cb18e6c254e13826e6bcfbfe95b819d77 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:26 -0300
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Subject: [PATCH 140/203] mtd: nand: pxa3xx: Use a completion to signal device
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ready
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The expected behavior of the waitfunc() NAND chip call is to wait
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for the device to be READY (this is a standard chip line).
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However, the current implementation does almost nothing, which opens
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the possibility of issuing a command to a non-ready device.
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Fix this by adding a new completion to wait for the ready event to arrive.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 38 ++++++++++++++++++++++++--------------
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1 file changed, 24 insertions(+), 14 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -37,6 +37,7 @@
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#include <linux/platform_data/mtd-nand-pxa3xx.h>
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+#define NAND_DEV_READY_TIMEOUT 50
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#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
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#define NAND_STOP_DELAY (2 * HZ/50)
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#define PAGE_CHUNK_SIZE (2048)
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@@ -168,7 +169,7 @@ struct pxa3xx_nand_info {
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struct clk *clk;
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void __iomem *mmio_base;
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unsigned long mmio_phys;
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- struct completion cmd_complete;
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+ struct completion cmd_complete, dev_ready;
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unsigned int buf_start;
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unsigned int buf_count;
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@@ -198,7 +199,7 @@ struct pxa3xx_nand_info {
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int use_ecc; /* use HW ECC ? */
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int use_dma; /* use DMA ? */
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int use_spare; /* use spare ? */
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- int is_ready;
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+ int need_wait;
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unsigned int fifo_size; /* max. data size in the FIFO */
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unsigned int data_size; /* data to be read from FIFO */
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@@ -480,7 +481,7 @@ static void start_data_dma(struct pxa3xx
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static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
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{
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struct pxa3xx_nand_info *info = devid;
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- unsigned int status, is_completed = 0;
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+ unsigned int status, is_completed = 0, is_ready = 0;
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unsigned int ready, cmd_done;
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if (info->cs == 0) {
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@@ -516,8 +517,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
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is_completed = 1;
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}
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if (status & ready) {
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- info->is_ready = 1;
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info->state = STATE_READY;
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+ is_ready = 1;
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}
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if (status & NDSR_WRCMDREQ) {
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@@ -546,6 +547,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
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nand_writel(info, NDSR, status);
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if (is_completed)
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complete(&info->cmd_complete);
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+ if (is_ready)
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+ complete(&info->dev_ready);
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NORMAL_IRQ_EXIT:
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return IRQ_HANDLED;
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}
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@@ -576,7 +579,6 @@ static int prepare_command_pool(struct p
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info->oob_size = 0;
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info->use_ecc = 0;
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info->use_spare = 1;
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- info->is_ready = 0;
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info->retcode = ERR_NONE;
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if (info->cs != 0)
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info->ndcb0 = NDCB0_CSEL;
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@@ -749,6 +751,8 @@ static void pxa3xx_nand_cmdfunc(struct m
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exec_cmd = prepare_command_pool(info, command, column, page_addr);
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if (exec_cmd) {
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init_completion(&info->cmd_complete);
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+ init_completion(&info->dev_ready);
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+ info->need_wait = 1;
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pxa3xx_nand_start(info);
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ret = wait_for_completion_timeout(&info->cmd_complete,
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@@ -863,21 +867,27 @@ static int pxa3xx_nand_waitfunc(struct m
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{
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struct pxa3xx_nand_host *host = mtd->priv;
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struct pxa3xx_nand_info *info = host->info_data;
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+ int ret;
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+
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+ if (info->need_wait) {
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+ ret = wait_for_completion_timeout(&info->dev_ready,
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+ CHIP_DELAY_TIMEOUT);
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+ info->need_wait = 0;
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+ if (!ret) {
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+ dev_err(&info->pdev->dev, "Ready time out!!!\n");
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+ return NAND_STATUS_FAIL;
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+ }
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+ }
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/* pxa3xx_nand_send_command has waited for command complete */
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if (this->state == FL_WRITING || this->state == FL_ERASING) {
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if (info->retcode == ERR_NONE)
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return 0;
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- else {
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- /*
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- * any error make it return 0x01 which will tell
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- * the caller the erase and write fail
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- */
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- return 0x01;
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- }
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+ else
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+ return NAND_STATUS_FAIL;
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}
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- return 0;
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+ return NAND_STATUS_READY;
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}
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static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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@@ -1030,7 +1040,7 @@ static int pxa3xx_nand_sensing(struct px
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return ret;
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chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
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- if (info->is_ready)
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+ if (!info->need_wait)
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return 0;
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return -ENODEV;
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