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40 lines
1.2 KiB
Diff
40 lines
1.2 KiB
Diff
From d6af8f27223a244d74ab44842bdec707c97cfe55 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Mon, 12 Aug 2013 14:14:48 -0300
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Subject: [PATCH 115/203] mtd: nand: pxa3xx: Handle ECC and DMA enable/disable
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properly
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When ECC is not selected, the ECC enable bit must be cleared
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in the NAND control register. Same applies to DMA.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa
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uint32_t ndcr;
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ndcr = host->reg_ndcr;
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- ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
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- ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
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+
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+ if (info->use_ecc)
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+ ndcr |= NDCR_ECC_EN;
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+ else
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+ ndcr &= ~NDCR_ECC_EN;
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+
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+ if (info->use_dma)
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+ ndcr |= NDCR_DMA_EN;
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+ else
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+ ndcr &= ~NDCR_DMA_EN;
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+
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ndcr |= NDCR_ND_RUN;
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/* clear status bits and run */
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