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358 lines
8.9 KiB
Diff
358 lines
8.9 KiB
Diff
From bcb0e54d62804f1f986ad478a11235dadb1b61bb Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Fri, 14 Jun 2013 10:44:57 -0300
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Subject: [PATCH 058/203] ARM: mvebu: Relocate Armada 370/XP DeviceBus device
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tree nodes
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Now that mbus has been added to the device tree, it's possible to
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move the DeviceBus out of internal registers, placing it directly
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below the mbus. This is a more accurate representation of the hardware.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Andrew Lunn <andrew@lunn.ch>
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Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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---
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arch/arm/boot/dts/armada-370-xp.dtsi | 94 +++++++++++++-----------
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arch/arm/boot/dts/armada-xp-db.dts | 59 +++++++--------
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arch/arm/boot/dts/armada-xp-gp.dts | 60 +++++++--------
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arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 60 +++++++--------
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4 files changed, 140 insertions(+), 133 deletions(-)
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--- a/arch/arm/boot/dts/armada-370-xp.dtsi
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+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
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@@ -36,6 +36,56 @@
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controller = <&mbusc>;
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interrupt-parent = <&mpic>;
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+ devbus-bootcs {
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+ compatible = "marvell,mvebu-devbus";
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+ reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&coreclk 0>;
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+ status = "disabled";
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+ };
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+
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+ devbus-cs0 {
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+ compatible = "marvell,mvebu-devbus";
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+ reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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+ ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&coreclk 0>;
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+ status = "disabled";
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+ };
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+
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+ devbus-cs1 {
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+ compatible = "marvell,mvebu-devbus";
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+ reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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+ ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&coreclk 0>;
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+ status = "disabled";
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+ };
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+
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+ devbus-cs2 {
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+ compatible = "marvell,mvebu-devbus";
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+ reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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+ ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&coreclk 0>;
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+ status = "disabled";
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+ };
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+
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+ devbus-cs3 {
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+ compatible = "marvell,mvebu-devbus";
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+ reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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+ ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&coreclk 0>;
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+ status = "disabled";
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+ };
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+
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -191,50 +241,6 @@
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status = "disabled";
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};
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- devbus-bootcs@10400 {
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- compatible = "marvell,mvebu-devbus";
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- reg = <0x10400 0x8>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- clocks = <&coreclk 0>;
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- status = "disabled";
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- };
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-
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- devbus-cs0@10408 {
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- compatible = "marvell,mvebu-devbus";
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- reg = <0x10408 0x8>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- clocks = <&coreclk 0>;
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- status = "disabled";
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- };
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-
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- devbus-cs1@10410 {
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- compatible = "marvell,mvebu-devbus";
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- reg = <0x10410 0x8>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- clocks = <&coreclk 0>;
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- status = "disabled";
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- };
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-
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- devbus-cs2@10418 {
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- compatible = "marvell,mvebu-devbus";
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- reg = <0x10418 0x8>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- clocks = <&coreclk 0>;
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- status = "disabled";
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- };
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-
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- devbus-cs3@10420 {
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- compatible = "marvell,mvebu-devbus";
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- reg = <0x10420 0x8>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- clocks = <&coreclk 0>;
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- status = "disabled";
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- };
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-db.dts
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+++ b/arch/arm/boot/dts/armada-xp-db.dts
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@@ -31,7 +31,36 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
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+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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+
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+ devbus-bootcs {
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+ status = "okay";
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+
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+ /* Device Bus parameters are required */
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+
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+ /* Read parameters */
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+ devbus,bus-width = <8>;
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+ devbus,turn-off-ps = <60000>;
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+ devbus,badr-skew-ps = <0>;
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+ devbus,acc-first-ps = <124000>;
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+ devbus,acc-next-ps = <248000>;
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+ devbus,rd-setup-ps = <0>;
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+ devbus,rd-hold-ps = <0>;
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+
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+ /* Write parameters */
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+ devbus,sync-enable = <0>;
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+ devbus,wr-high-ps = <60000>;
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+ devbus,wr-low-ps = <60000>;
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+ devbus,ale-wr-ps = <60000>;
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+
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+ /* NOR 16 MiB */
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+ nor@0 {
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+ compatible = "cfi-flash";
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+ reg = <0 0x1000000>;
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+ bank-width = <2>;
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+ };
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+ };
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internal-regs {
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serial@12000 {
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@@ -160,34 +189,6 @@
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};
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};
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- devbus-bootcs@10400 {
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- status = "okay";
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- ranges = <0 0xf0000000 0x1000000>;
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-
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- /* Device Bus parameters are required */
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-
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- /* Read parameters */
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- devbus,bus-width = <8>;
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- devbus,turn-off-ps = <60000>;
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- devbus,badr-skew-ps = <0>;
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- devbus,acc-first-ps = <124000>;
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- devbus,acc-next-ps = <248000>;
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- devbus,rd-setup-ps = <0>;
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- devbus,rd-hold-ps = <0>;
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-
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- /* Write parameters */
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- devbus,sync-enable = <0>;
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- devbus,wr-high-ps = <60000>;
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- devbus,wr-low-ps = <60000>;
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- devbus,ale-wr-ps = <60000>;
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-
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- /* NOR 16 MiB */
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- nor@0 {
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- compatible = "cfi-flash";
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- reg = <0 0x1000000>;
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- bank-width = <2>;
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- };
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- };
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};
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-gp.dts
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+++ b/arch/arm/boot/dts/armada-xp-gp.dts
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@@ -40,7 +40,36 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
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+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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+
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+ devbus-bootcs {
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+ status = "okay";
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+
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+ /* Device Bus parameters are required */
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+
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+ /* Read parameters */
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+ devbus,bus-width = <8>;
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+ devbus,turn-off-ps = <60000>;
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+ devbus,badr-skew-ps = <0>;
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+ devbus,acc-first-ps = <124000>;
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+ devbus,acc-next-ps = <248000>;
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+ devbus,rd-setup-ps = <0>;
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+ devbus,rd-hold-ps = <0>;
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+
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+ /* Write parameters */
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+ devbus,sync-enable = <0>;
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+ devbus,wr-high-ps = <60000>;
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+ devbus,wr-low-ps = <60000>;
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+ devbus,ale-wr-ps = <60000>;
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+
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+ /* NOR 16 MiB */
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+ nor@0 {
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+ compatible = "cfi-flash";
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+ reg = <0 0x1000000>;
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+ bank-width = <2>;
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+ };
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+ };
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internal-regs {
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serial@12000 {
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@@ -126,35 +155,6 @@
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};
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};
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- devbus-bootcs@10400 {
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- status = "okay";
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- ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
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-
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- /* Device Bus parameters are required */
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-
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- /* Read parameters */
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- devbus,bus-width = <8>;
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- devbus,turn-off-ps = <60000>;
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- devbus,badr-skew-ps = <0>;
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- devbus,acc-first-ps = <124000>;
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- devbus,acc-next-ps = <248000>;
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- devbus,rd-setup-ps = <0>;
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- devbus,rd-hold-ps = <0>;
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-
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- /* Write parameters */
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- devbus,sync-enable = <0>;
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- devbus,wr-high-ps = <60000>;
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- devbus,wr-low-ps = <60000>;
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- devbus,ale-wr-ps = <60000>;
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-
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- /* NOR 16 MiB */
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- nor@0 {
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- compatible = "cfi-flash";
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- reg = <0 0x1000000>;
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- bank-width = <2>;
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- };
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- };
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-
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pcie-controller {
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status = "okay";
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--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
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+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
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@@ -28,7 +28,36 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
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+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
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+
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+ devbus-bootcs {
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+ status = "okay";
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+
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+ /* Device Bus parameters are required */
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+
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+ /* Read parameters */
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+ devbus,bus-width = <8>;
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+ devbus,turn-off-ps = <60000>;
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+ devbus,badr-skew-ps = <0>;
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+ devbus,acc-first-ps = <124000>;
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+ devbus,acc-next-ps = <248000>;
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+ devbus,rd-setup-ps = <0>;
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+ devbus,rd-hold-ps = <0>;
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+
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+ /* Write parameters */
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+ devbus,sync-enable = <0>;
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+ devbus,wr-high-ps = <60000>;
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+ devbus,wr-low-ps = <60000>;
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+ devbus,ale-wr-ps = <60000>;
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+
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+ /* NOR 128 MiB */
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+ nor@0 {
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+ compatible = "cfi-flash";
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+ reg = <0 0x8000000>;
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+ bank-width = <2>;
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+ };
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+ };
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internal-regs {
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serial@12000 {
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@@ -144,35 +173,6 @@
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status = "okay";
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};
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- devbus-bootcs@10400 {
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- status = "okay";
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- ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
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-
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- /* Device Bus parameters are required */
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-
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- /* Read parameters */
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- devbus,bus-width = <8>;
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- devbus,turn-off-ps = <60000>;
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- devbus,badr-skew-ps = <0>;
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- devbus,acc-first-ps = <124000>;
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- devbus,acc-next-ps = <248000>;
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- devbus,rd-setup-ps = <0>;
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- devbus,rd-hold-ps = <0>;
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-
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- /* Write parameters */
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- devbus,sync-enable = <0>;
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- devbus,wr-high-ps = <60000>;
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- devbus,wr-low-ps = <60000>;
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- devbus,ale-wr-ps = <60000>;
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-
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- /* NOR 128 MiB */
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- nor@0 {
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- compatible = "cfi-flash";
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- reg = <0 0x8000000>;
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- bank-width = <2>;
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- };
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- };
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-
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pcie-controller {
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status = "okay";
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/* Internal mini-PCIe connector */
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