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185 lines
5.7 KiB
Diff
185 lines
5.7 KiB
Diff
From 90b1f963b07d05e8243e5053a910e8a47222f7a1 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Fri, 5 Jul 2013 14:54:17 +0200
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Subject: [PATCH 047/203] PCI: mvebu: Adapt to the new device tree layout
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The new device tree layout encodes the window's target ID and attribute
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in the PCIe controller node's ranges property. This allows to parse
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such entries to obtain such information and use the recently introduced
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MBus API to create the windows, instead of using the current name based
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scheme.
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Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Tested-by: Andrew Lunn <andrew@lunn.ch>
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Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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---
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drivers/pci/host/pci-mvebu.c | 113 ++++++++++++++++++++++++++++++++-----------
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1 file changed, 84 insertions(+), 29 deletions(-)
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -119,6 +119,10 @@ struct mvebu_pcie_port {
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u32 port;
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u32 lane;
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int devfn;
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+ unsigned int mem_target;
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+ unsigned int mem_attr;
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+ unsigned int io_target;
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+ unsigned int io_attr;
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struct clk *clk;
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struct mvebu_sw_pci_bridge bridge;
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struct device_node *dn;
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@@ -303,10 +307,9 @@ static void mvebu_pcie_handle_iobase_cha
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(port->bridge.iolimitupper << 16)) -
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iobase);
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- mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
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- port->iowin_size,
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- iobase,
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- MVEBU_MBUS_PCI_IO);
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+ mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
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+ port->iowin_base, port->iowin_size,
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+ iobase);
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pci_ioremap_io(iobase, port->iowin_base);
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}
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@@ -338,10 +341,8 @@ static void mvebu_pcie_handle_membase_ch
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(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
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port->memwin_base;
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- mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
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- port->memwin_size,
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- MVEBU_MBUS_NO_REMAP,
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- MVEBU_MBUS_PCI_MEM);
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+ mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
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+ port->memwin_base, port->memwin_size);
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}
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/*
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@@ -730,12 +731,54 @@ mvebu_pcie_map_registers(struct platform
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return devm_request_and_ioremap(&pdev->dev, ®s);
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}
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+#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
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+#define DT_TYPE_IO 0x1
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+#define DT_TYPE_MEM32 0x2
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+#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
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+#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
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+
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+static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
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+ unsigned long type, int *tgt, int *attr)
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+{
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+ const int na = 3, ns = 2;
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+ const __be32 *range;
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+ int rlen, nranges, rangesz, pna, i;
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+
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+ range = of_get_property(np, "ranges", &rlen);
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+ if (!range)
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+ return -EINVAL;
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+
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+ pna = of_n_addr_cells(np);
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+ rangesz = pna + na + ns;
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+ nranges = rlen / sizeof(__be32) / rangesz;
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+
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+ for (i = 0; i < nranges; i++) {
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+ u32 flags = of_read_number(range, 1);
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+ u32 slot = of_read_number(range, 2);
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+ u64 cpuaddr = of_read_number(range + na, pna);
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+ unsigned long rtype;
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+
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+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
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+ rtype = IORESOURCE_IO;
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+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
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+ rtype = IORESOURCE_MEM;
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+
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+ if (slot == PCI_SLOT(devfn) && type == rtype) {
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+ *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
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+ *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
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+ return 0;
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+ }
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+
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+ range += rangesz;
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+ }
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+
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+ return -ENOENT;
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+}
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+
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static int __init mvebu_pcie_probe(struct platform_device *pdev)
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{
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struct mvebu_pcie *pcie;
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struct device_node *np = pdev->dev.of_node;
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- struct of_pci_range range;
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- struct of_pci_range_parser parser;
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struct device_node *child;
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int i, ret;
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@@ -746,29 +789,25 @@ static int __init mvebu_pcie_probe(struc
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pcie->pdev = pdev;
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- if (of_pci_range_parser_init(&parser, np))
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+ /* Get the PCIe memory and I/O aperture */
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+ mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
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+ if (resource_size(&pcie->mem) == 0) {
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+ dev_err(&pdev->dev, "invalid memory aperture size\n");
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return -EINVAL;
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+ }
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- /* Get the I/O and memory ranges from DT */
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- for_each_of_pci_range(&parser, &range) {
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- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
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- if (restype == IORESOURCE_IO) {
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- of_pci_range_to_resource(&range, np, &pcie->io);
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- of_pci_range_to_resource(&range, np, &pcie->realio);
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- pcie->io.name = "I/O";
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- pcie->realio.start = max_t(resource_size_t,
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- PCIBIOS_MIN_IO,
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- range.pci_addr);
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- pcie->realio.end = min_t(resource_size_t,
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- IO_SPACE_LIMIT,
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- range.pci_addr + range.size);
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- }
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- if (restype == IORESOURCE_MEM) {
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- of_pci_range_to_resource(&range, np, &pcie->mem);
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- pcie->mem.name = "MEM";
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- }
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+ mvebu_mbus_get_pcie_io_aperture(&pcie->io);
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+ if (resource_size(&pcie->io) == 0) {
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+ dev_err(&pdev->dev, "invalid I/O aperture size\n");
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+ return -EINVAL;
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}
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+ pcie->realio.flags = pcie->io.flags;
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+ pcie->realio.start = PCIBIOS_MIN_IO;
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+ pcie->realio.end = min_t(resource_size_t,
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+ IO_SPACE_LIMIT,
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+ resource_size(&pcie->io));
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+
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/* Get the bus range */
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ret = of_pci_parse_bus_range(np, &pcie->busn);
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if (ret) {
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@@ -816,6 +855,22 @@ static int __init mvebu_pcie_probe(struc
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if (port->devfn < 0)
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continue;
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+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
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+ &port->mem_target, &port->mem_attr);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
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+ port->port, port->lane);
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+ continue;
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+ }
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+
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+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
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+ &port->io_target, &port->io_attr);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
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+ port->port, port->lane);
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+ continue;
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+ }
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+
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port->base = mvebu_pcie_map_registers(pdev, child, port);
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if (!port->base) {
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dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
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