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212 lines
6.9 KiB
Diff
212 lines
6.9 KiB
Diff
From 031573a8a1e73b0ac548812c10c3e426c2b4ce61 Mon Sep 17 00:00:00 2001
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From: Yuantian Tang <andy.tang@nxp.com>
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Date: Tue, 15 Oct 2019 20:08:58 +0800
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Subject: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support
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Thermal Monitor Unit v2 is introduced on new Layscape SoC.
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Compared to v1, TMUv2 has a little different register layout
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and digital output is fairly linear.
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Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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---
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drivers/thermal/qoriq_thermal.c | 118 ++++++++++++++++++++++++++++++++--------
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1 file changed, 96 insertions(+), 22 deletions(-)
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--- a/drivers/thermal/qoriq_thermal.c
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+++ b/drivers/thermal/qoriq_thermal.c
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@@ -16,6 +16,15 @@
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#define SITES_MAX 16
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#define TMU_TEMP_PASSIVE_COOL_DELTA 10000
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+#define TMR_DISABLE 0x0
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+#define TMR_ME 0x80000000
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+#define TMR_ALPF 0x0c000000
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+#define TMR_ALPF_V2 0x03000000
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+#define TMTMIR_DEFAULT 0x0000000f
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+#define TIER_DISABLE 0x0
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+#define TEUMR0_V2 0x51009c00
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+#define TMU_VER1 0x1
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+#define TMU_VER2 0x2
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/*
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* QorIQ TMU Registers
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@@ -26,17 +35,12 @@ struct qoriq_tmu_site_regs {
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u8 res0[0x8];
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};
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-struct qoriq_tmu_regs {
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+struct qoriq_tmu_regs_v1 {
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u32 tmr; /* Mode Register */
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-#define TMR_DISABLE 0x0
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-#define TMR_ME 0x80000000
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-#define TMR_ALPF 0x0c000000
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u32 tsr; /* Status Register */
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u32 tmtmir; /* Temperature measurement interval Register */
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-#define TMTMIR_DEFAULT 0x0000000f
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u8 res0[0x14];
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u32 tier; /* Interrupt Enable Register */
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-#define TIER_DISABLE 0x0
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u32 tidr; /* Interrupt Detect Register */
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u32 tiscr; /* Interrupt Site Capture Register */
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u32 ticscr; /* Interrupt Critical Site Capture Register */
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@@ -56,12 +60,52 @@ struct qoriq_tmu_regs {
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u32 ipbrr0; /* IP Block Revision Register 0 */
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u32 ipbrr1; /* IP Block Revision Register 1 */
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u8 res6[0x310];
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- u32 ttr0cr; /* Temperature Range 0 Control Register */
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- u32 ttr1cr; /* Temperature Range 1 Control Register */
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- u32 ttr2cr; /* Temperature Range 2 Control Register */
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- u32 ttr3cr; /* Temperature Range 3 Control Register */
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+ u32 ttrcr[4]; /* Temperature Range Control Register */
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};
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+struct qoriq_tmu_regs_v2 {
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+ u32 tmr; /* Mode Register */
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+ u32 tsr; /* Status Register */
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+ u32 tmsr; /* monitor site register */
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+ u32 tmtmir; /* Temperature measurement interval Register */
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+ u8 res0[0x10];
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+ u32 tier; /* Interrupt Enable Register */
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+ u32 tidr; /* Interrupt Detect Register */
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+ u8 res1[0x8];
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+ u32 tiiscr; /* interrupt immediate site capture register */
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+ u32 tiascr; /* interrupt average site capture register */
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+ u32 ticscr; /* Interrupt Critical Site Capture Register */
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+ u32 res2;
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+ u32 tmhtcr; /* monitor high temperature capture register */
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+ u32 tmltcr; /* monitor low temperature capture register */
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+ u32 tmrtrcr; /* monitor rising temperature rate capture register */
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+ u32 tmftrcr; /* monitor falling temperature rate capture register */
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+ u32 tmhtitr; /* High Temperature Immediate Threshold */
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+ u32 tmhtatr; /* High Temperature Average Threshold */
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+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
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+ u32 res3;
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+ u32 tmltitr; /* monitor low temperature immediate threshold */
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+ u32 tmltatr; /* monitor low temperature average threshold register */
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+ u32 tmltactr; /* monitor low temperature average critical threshold */
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+ u32 res4;
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+ u32 tmrtrctr; /* monitor rising temperature rate critical threshold */
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+ u32 tmftrctr; /* monitor falling temperature rate critical threshold*/
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+ u8 res5[0x8];
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+ u32 ttcfgr; /* Temperature Configuration Register */
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+ u32 tscfgr; /* Sensor Configuration Register */
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+ u8 res6[0x78];
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+ struct qoriq_tmu_site_regs site[SITES_MAX];
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+ u8 res7[0x9f8];
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+ u32 ipbrr0; /* IP Block Revision Register 0 */
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+ u32 ipbrr1; /* IP Block Revision Register 1 */
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+ u8 res8[0x300];
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+ u32 teumr0;
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+ u32 teumr1;
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+ u32 teumr2;
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+ u32 res9;
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+ u32 ttrcr[4]; /* Temperature Range Control Register */
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+ };
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+
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struct qoriq_tmu_data;
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/*
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@@ -77,7 +121,9 @@ struct qoriq_sensor {
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};
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struct qoriq_tmu_data {
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- struct qoriq_tmu_regs __iomem *regs;
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+ int ver;
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+ struct qoriq_tmu_regs_v1 __iomem *regs;
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+ struct qoriq_tmu_regs_v2 __iomem *regs_v2;
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struct clk *clk;
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bool little_endian;
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struct qoriq_sensor *sensor[SITES_MAX];
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@@ -210,12 +256,23 @@ static int qoriq_tmu_register_tmu_zone(s
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qdata->sensor[id]->temp_critical = trip[1].temperature;
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}
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- sites |= 0x1 << (15 - id);
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+ if (qdata->ver == TMU_VER1)
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+ sites |= 0x1 << (15 - id);
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+ else
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+ sites |= 0x1 << id;
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}
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/* Enable monitoring */
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- if (sites != 0)
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- tmu_write(qdata, sites | TMR_ME | TMR_ALPF, &qdata->regs->tmr);
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+ if (sites != 0) {
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+ if (qdata->ver == TMU_VER1) {
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+ tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
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+ &qdata->regs->tmr);
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+ } else {
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+ tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
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+ tmu_write(qdata, TMR_ME | TMR_ALPF_V2,
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+ &qdata->regs_v2->tmr);
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+ }
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+ }
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return 0;
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}
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@@ -228,16 +285,21 @@ static int qoriq_tmu_calibration(struct
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struct device_node *np = pdev->dev.of_node;
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struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
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- if (of_property_read_u32_array(np, "fsl,tmu-range", range, 4)) {
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- dev_err(&pdev->dev, "missing calibration range.\n");
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- return -ENODEV;
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+ len = of_property_count_u32_elems(np, "fsl,tmu-range");
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+ if (len < 0 || len > 4) {
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+ dev_err(&pdev->dev, "invalid range data.\n");
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+ return len;
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+ }
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+
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+ val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
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+ if (val != 0) {
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+ dev_err(&pdev->dev, "failed to read range data.\n");
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+ return val;
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}
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/* Init temperature range registers */
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- tmu_write(data, range[0], &data->regs->ttr0cr);
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- tmu_write(data, range[1], &data->regs->ttr1cr);
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- tmu_write(data, range[2], &data->regs->ttr2cr);
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- tmu_write(data, range[3], &data->regs->ttr3cr);
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+ for (i = 0; i < len; i++)
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+ tmu_write(data, range[i], &data->regs->ttrcr[i]);
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calibration = of_get_property(np, "fsl,tmu-calibration", &len);
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if (calibration == NULL || len % 8) {
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@@ -261,7 +323,12 @@ static void qoriq_tmu_init_device(struct
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tmu_write(data, TIER_DISABLE, &data->regs->tier);
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/* Set update_interval */
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- tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
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+ if (data->ver == TMU_VER1) {
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+ tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
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+ } else {
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+ tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
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+ tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
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+ }
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/* Disable monitoring */
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tmu_write(data, TMR_DISABLE, &data->regs->tmr);
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@@ -270,6 +337,7 @@ static void qoriq_tmu_init_device(struct
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static int qoriq_tmu_probe(struct platform_device *pdev)
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{
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int ret;
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+ u32 ver;
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struct qoriq_tmu_data *data;
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struct device_node *np = pdev->dev.of_node;
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@@ -298,6 +366,12 @@ static int qoriq_tmu_probe(struct platfo
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return ret;
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}
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+ /* version register offset at: 0xbf8 on both v1 and v2 */
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+ ver = tmu_read(data, &data->regs->ipbrr0);
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+ data->ver = (ver >> 8) & 0xff;
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+ if (data->ver == TMU_VER2)
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+ data->regs_v2 = (void __iomem *)data->regs;
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+
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qoriq_tmu_init_device(data); /* TMU initialization */
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ret = qoriq_tmu_calibration(pdev); /* TMU calibration */
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