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171 lines
5.3 KiB
Diff
171 lines
5.3 KiB
Diff
From 9050c0619cdf5399d19e3683d6fb1db355dda110 Mon Sep 17 00:00:00 2001
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From: Robin Gong <yibin.gong@nxp.com>
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Date: Wed, 17 Apr 2019 17:05:42 +0800
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Subject: [PATCH] MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for
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each channel
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Add power domains for each dma channel so that edma channel could
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know the power state of every dma channel anytime and clear easily
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unexpected interrupt which triggered before the last partition reset.
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Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
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(cherry picked from commit 0b6da46b7bdb2284e24757d48466268b9feb5b7c)
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---
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.../devicetree/bindings/dma/fsl-edma-v3.txt | 11 +++-
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drivers/dma/fsl-edma-v3.c | 58 +++++++++++++++++++++-
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2 files changed, 67 insertions(+), 2 deletions(-)
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--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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@@ -30,6 +30,8 @@ Required properties:
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0: not dual fifo case, 1: dualfifo case.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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+- power-domains: Power domains for edma channel used.
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+- power-domain-names: Power domains name for edma channel used.
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Examples:
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edma0: dma-controller@40018000 {
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@@ -46,6 +48,12 @@ edma0: dma-controller@40018000 {
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
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"edma0-chan14-rx", "edma0-chan15-tx";
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+ power-domains = <&pd IMX_SC_R_DMA_0_CH12>,
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+ <&pd IMX_SC_R_DMA_0_CH13>,
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+ <&pd IMX_SC_R_DMA_0_CH14>,
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+ <&pd IMX_SC_R_DMA_0_CH15>;
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+ power-domain-names = "edma0-chan12", "edma0-chan13",
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+ "edma0-chan14", "edma0-chan15";
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status = "okay";
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};
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@@ -65,7 +73,8 @@ lpuart1: serial@5a070000 {
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clock-names = "ipg";
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assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
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assigned-clock-rates = <80000000>;
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- power-domains = <&pd_dma_lpuart1>;
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+ power-domains = <&pd IMX_SC_R_UART_1>,
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+ power-domain-names = "uart";
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dma-names = "tx","rx";
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dmas = <&edma0 15 0 0>,
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<&edma0 14 0 1>;
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--- a/drivers/dma/fsl-edma-v3.c
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+++ b/drivers/dma/fsl-edma-v3.c
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@@ -27,6 +27,8 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_dma.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/pm_domain.h>
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#include "virt-dma.h"
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@@ -164,6 +166,7 @@ struct fsl_edma3_chan {
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u32 chn_real_count;
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char txirq_name[32];
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struct platform_device *pdev;
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+ struct device *dev;
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};
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struct fsl_edma3_desc {
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@@ -798,8 +801,10 @@ static int fsl_edma3_alloc_chan_resource
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fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
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sizeof(struct fsl_edma3_hw_tcd),
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32, 0);
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+ pm_runtime_get_sync(fsl_chan->dev);
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/* clear meaningless pending irq anyway */
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writel(1, fsl_chan->membase + EDMA_CH_INT);
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+
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ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
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fsl_edma3_tx_handler, fsl_chan->edma3->irqflag,
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fsl_chan->txirq_name, fsl_chan);
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@@ -830,6 +835,7 @@ static void fsl_edma3_free_chan_resource
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dma_pool_destroy(fsl_chan->tcd_pool);
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fsl_chan->tcd_pool = NULL;
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fsl_chan->used = false;
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+ pm_runtime_put_sync(fsl_chan->dev);
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}
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static void fsl_edma3_synchronize(struct dma_chan *chan)
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@@ -839,6 +845,37 @@ static void fsl_edma3_synchronize(struct
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vchan_synchronize(&fsl_chan->vchan);
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}
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+static struct device *fsl_edma3_attach_pd(struct device *dev,
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+ struct device_node *np, int index)
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+{
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+ const char *domn = "edma0-chan01";
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+ struct device *pd_chan;
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+ struct device_link *link;
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+ int ret;
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+
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+ ret = of_property_read_string_index(np, "power-domain-names", index,
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+ &domn);
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+ if (ret) {
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+ dev_err(dev, "parse power-domain-names error.(%d)\n", ret);
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+ return NULL;
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+ }
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+
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+ pd_chan = dev_pm_domain_attach_by_name(dev, domn);
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+ if (!pd_chan)
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+ return NULL;
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+
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+ link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
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+ DL_FLAG_PM_RUNTIME |
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+ DL_FLAG_RPM_ACTIVE);
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+ if (IS_ERR(link)) {
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+ dev_err(dev, "Failed to add device_link to %s: %ld\n", domn,
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+ PTR_ERR(link));
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+ return NULL;
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+ }
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+
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+ return pd_chan;
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+}
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+
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static int fsl_edma3_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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@@ -962,6 +999,22 @@ static int fsl_edma3_probe(struct platfo
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dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n");
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return ret;
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}
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+ /* Attach power domains from dts for each dma chanel device */
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+ for (i = 0; i < fsl_edma3->n_chans; i++) {
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+ struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i];
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+ struct device *dev;
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+
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+ dev = fsl_edma3_attach_pd(&pdev->dev, np, i);
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+ if (!dev) {
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+ dev_err(dev, "edma channel attach failed.\n");
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+ return -EINVAL;
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+ }
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+
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+ fsl_chan->dev = dev;
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+ /* clear meaningless pending irq anyway */
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+ writel(1, fsl_chan->membase + EDMA_CH_INT);
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+ pm_runtime_put_sync(dev);
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+ }
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ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3);
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if (ret) {
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@@ -970,6 +1023,9 @@ static int fsl_edma3_probe(struct platfo
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return ret;
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}
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+ pm_runtime_dont_use_autosuspend(&pdev->dev);
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+ pm_runtime_enable(&pdev->dev);
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+
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return 0;
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}
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@@ -1068,7 +1124,7 @@ static int __init fsl_edma3_init(void)
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{
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return platform_driver_register(&fsl_edma3_driver);
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}
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-subsys_initcall(fsl_edma3_init);
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+fs_initcall(fsl_edma3_init);
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static void __exit fsl_edma3_exit(void)
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{
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