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59 lines
1.6 KiB
Diff
59 lines
1.6 KiB
Diff
From 7d11e6c1669b9134b11a48cdf47e5b7ab1b2396c Mon Sep 17 00:00:00 2001
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From: Bing Song <bing.song@nxp.com>
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Date: Fri, 5 Jan 2018 08:33:51 +0200
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Subject: [PATCH] MLK-17368-1 drm: add fourcc codes for Verisilicon tiled
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formats
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These formats will be used by VPU and DCSS.
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Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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[ Aisheng : VENDOR_VSI changed to 0xf1 ]
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Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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---
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include/uapi/drm/drm_fourcc.h | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/include/uapi/drm/drm_fourcc.h
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+++ b/include/uapi/drm/drm_fourcc.h
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@@ -310,6 +310,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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#define DRM_FORMAT_MOD_VENDOR_AMPHION 0xf0
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+#define DRM_FORMAT_MOD_VENDOR_VSI 0xf1
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/* add more to the end as needed */
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@@ -767,6 +768,32 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_AMPHION_TILED fourcc_mod_code(AMPHION, 1)
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+/* Verisilicon framebuffer modifiers */
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+
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+/*
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+ * Verisilicon 8x4 tiling layout
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+ *
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+ * This is G1 VPU tiled layout using tiles of 8x4 pixels in a row-major
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+ * layout.
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+ */
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+#define DRM_FORMAT_MOD_VSI_G1_TILED fourcc_mod_code(VSI, 1)
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+
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+/*
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+ * Verisilicon 4x4 tiling layout
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+ *
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+ * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major
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+ * layout.
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+ */
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+#define DRM_FORMAT_MOD_VSI_G2_TILED fourcc_mod_code(VSI, 2)
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+
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+/*
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+ * Verisilicon 4x4 tiling with compression layout
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+ *
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+ * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major
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+ * layout with compression.
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+ */
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+#define DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED fourcc_mod_code(VSI, 3)
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+
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#if defined(__cplusplus)
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}
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#endif
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