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193 lines
6.3 KiB
Diff
193 lines
6.3 KiB
Diff
From 2a07ee2b9608e665872e7d83bebd3acb7e45c2e6 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Sat, 9 Nov 2019 15:02:51 +0200
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Subject: [PATCH] net: mscc: ocelot: change prototypes of switchdev port
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attribute handlers
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This is needed so that the Felix DSA front-end can call the Ocelot
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implementations.
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The implementation of the "mc_disabled" switchdev attribute has also
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been simplified by using the read-modify-write macro instead of
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open-coding that operation.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mscc/ocelot.c | 88 +++++++++++++++++++-------------------
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1 file changed, 45 insertions(+), 43 deletions(-)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -1285,26 +1285,20 @@ static const struct ethtool_ops ocelot_e
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.get_ts_info = ocelot_get_ts_info,
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};
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-static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
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- struct switchdev_trans *trans,
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- u8 state)
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+static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
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+ u8 state)
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{
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- struct ocelot *ocelot = ocelot_port->ocelot;
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u32 port_cfg;
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- int port, i;
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-
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- if (switchdev_trans_ph_prepare(trans))
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- return 0;
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+ int p, i;
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- if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
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- return 0;
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+ if (!(BIT(port) & ocelot->bridge_mask))
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+ return;
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- port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
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- ocelot_port->chip_port);
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+ port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
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switch (state) {
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case BR_STATE_FORWARDING:
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- ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
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+ ocelot->bridge_fwd_mask |= BIT(port);
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/* Fallthrough */
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case BR_STATE_LEARNING:
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port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
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@@ -1312,19 +1306,18 @@ static int ocelot_port_attr_stp_state_se
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default:
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port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
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- ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
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+ ocelot->bridge_fwd_mask &= ~BIT(port);
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break;
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}
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- ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
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- ocelot_port->chip_port);
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+ ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
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/* Apply FWD mask. The loop is needed to add/remove the current port as
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* a source for the other ports.
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*/
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- for (port = 0; port < ocelot->num_phys_ports; port++) {
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- if (ocelot->bridge_fwd_mask & BIT(port)) {
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- unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
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+ for (p = 0; p < ocelot->num_phys_ports; p++) {
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+ if (ocelot->bridge_fwd_mask & BIT(p)) {
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+ unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
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for (i = 0; i < ocelot->num_phys_ports; i++) {
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unsigned long bond_mask = ocelot->lags[i];
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@@ -1332,7 +1325,7 @@ static int ocelot_port_attr_stp_state_se
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if (!bond_mask)
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continue;
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- if (bond_mask & BIT(port)) {
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+ if (bond_mask & BIT(p)) {
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mask &= ~bond_mask;
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break;
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}
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@@ -1340,47 +1333,55 @@ static int ocelot_port_attr_stp_state_se
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ocelot_write_rix(ocelot,
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BIT(ocelot->num_phys_ports) | mask,
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- ANA_PGID_PGID, PGID_SRC + port);
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+ ANA_PGID_PGID, PGID_SRC + p);
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} else {
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/* Only the CPU port, this is compatible with link
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* aggregation.
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*/
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ocelot_write_rix(ocelot,
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BIT(ocelot->num_phys_ports),
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- ANA_PGID_PGID, PGID_SRC + port);
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+ ANA_PGID_PGID, PGID_SRC + p);
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}
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}
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+}
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+
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+static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
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+ struct switchdev_trans *trans,
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+ u8 state)
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+{
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+ if (switchdev_trans_ph_prepare(trans))
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+ return;
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- return 0;
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+ ocelot_bridge_stp_state_set(ocelot, port, state);
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}
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-static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
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+static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
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+{
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+ ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
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+ ANA_AUTOAGE);
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+}
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+
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+static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
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unsigned long ageing_clock_t)
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{
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- struct ocelot *ocelot = ocelot_port->ocelot;
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unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
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u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
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- ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
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- ANA_AUTOAGE);
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+ ocelot_set_ageing_time(ocelot, ageing_time);
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}
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-static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
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+static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc)
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{
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- struct ocelot *ocelot = port->ocelot;
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- u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
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- port->chip_port);
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+ u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
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+ ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
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+ ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
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+ u32 val = 0;
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if (mc)
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- val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
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- ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
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- ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
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- else
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- val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
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- ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
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- ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
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+ val = cpu_fwd_mcast;
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- ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
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+ ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast,
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+ ANA_PORT_CPU_FWD_CFG, port);
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}
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static int ocelot_port_attr_set(struct net_device *dev,
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@@ -1389,22 +1390,23 @@ static int ocelot_port_attr_set(struct n
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{
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struct ocelot_port *ocelot_port = netdev_priv(dev);
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struct ocelot *ocelot = ocelot_port->ocelot;
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+ int port = ocelot_port->chip_port;
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int err = 0;
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switch (attr->id) {
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case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
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- ocelot_port_attr_stp_state_set(ocelot_port, trans,
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+ ocelot_port_attr_stp_state_set(ocelot, port, trans,
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attr->u.stp_state);
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break;
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case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
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- ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
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+ ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time);
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break;
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case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
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- ocelot_port_vlan_filtering(ocelot, ocelot_port->chip_port,
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+ ocelot_port_vlan_filtering(ocelot, port,
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attr->u.vlan_filtering);
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break;
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case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
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- ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
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+ ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled);
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break;
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default:
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err = -EOPNOTSUPP;
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