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462 lines
11 KiB
Diff
462 lines
11 KiB
Diff
From 8fd1ab38e922383fa87db60c48c44ab0d5e6f1c1 Mon Sep 17 00:00:00 2001
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From: Li Yang <leoyang.li@nxp.com>
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Date: Thu, 2 May 2019 15:52:49 -0500
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Subject: [PATCH] arm64: dts: ls1012a: accumulated change for ls1012a boards
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commit 65c558ec270003e8e99cb58c940d3b913d08fa39
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Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Date: Tue May 15 08:47:19 2018 +0800
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arm64: dts: ls1012a: correct the register range of dcfg
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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commit 8f7b4cded4ea1fca53516ae8f5d5bc89af291f26
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Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Date: Mon May 7 11:52:04 2018 +0530
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arm64: dts: ls1012a: Add LS1012A-FRWY board support
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LS1012A-FRWY is a different design from LS1012A-FRDM,
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but has some common SoC features. Key feature on this
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board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
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QuadSPI, Audio, UART.
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Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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commit 94fc77837b3b6f4213a49b29ddc3e09e38ae5fbb
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Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Date: Mon Apr 2 16:16:47 2018 +0800
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arm64: dts: ls1012a: add dts entry for A-010650
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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commit d4164a6d8cffd8f09c451073754834d58b7ace19
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Author: Suresh Gupta <suresh.gupta@nxp.com>
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Date: Thu Feb 1 23:44:15 2018 +0530
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arm64: dts: freescale: ls1012a: Add DT nodes for qspi
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Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
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Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
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commit 4fdc98a03492b732a48426a4180f7d6a36847e71
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Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Date: Wed Nov 1 10:31:47 2017 +0800
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arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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commit bb534725996b92aff853a4dee43738629fd4ac08
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Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Date: Wed Nov 29 06:31:23 2017 +0530
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arm64: dts: freescale: ls1012a: Disable PCIe node as default
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Keep PCIe node in "disabled" status as SoC default.
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Only enable it for boards with PCIe circuit designed,
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such as LS1012ARDB and LS1012AQDS.
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Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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commit 6b9a3244baba2c5126f349800ecaad83ba97ee47
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Author: Calvin Johnson <calvin.johnson@nxp.com>
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Date: Mon Oct 16 12:25:19 2017 +0530
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arm64: dts: freescale: ls1012a: fix RGMII tx delay issue
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Recently logic to enable RGMII tx delay was changed by
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below patch.
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https://patchwork.kernel.org/patch/9447581/
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Based on the patch, enabling tx delay again using rgmii-txid.
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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commit 1e17e247088f6e2c08041559e38053b70a9d2bbe
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Author: Calvin Johnson <calvin.johnson@nxp.com>
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Date: Sat Sep 16 14:20:23 2017 +0530
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arm64: dts: freescale: ls1012a: update with pppfe support
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Update ls1012a dtsi and platform dts files with
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support for ppfe.
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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commit e9661ed864d2a9d437057f97729410bb9af994f2
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Author: Suresh Gupta <suresh.gupta@nxp.com>
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Date: Tue May 16 17:17:21 2017 +0530
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arm64: dts: ls1012a: add the DTS node for QSPI support
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There is a s25fs512s qspi flash on QDS, RDB and FRDM board.
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Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
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commit ed9c51239461fe0322da2e93f50033ea0d05bc4f
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Author: Chenhui Zhao <chenhui.zhao@nxp.com>
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Date: Fri May 5 17:45:15 2017 +0800
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arm64: dts: ls1012a: add ftm0 node
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 58 ++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 62 ++++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 62 ++++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 68 +++++++++++++++++++++-
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4 files changed, 248 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
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@@ -13,6 +13,11 @@
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model = "LS1012A Freedom Board";
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compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+
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sys_mclk: clock-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -74,6 +79,44 @@
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};
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};
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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&sai2 {
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status = "okay";
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};
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@@ -81,3 +124,18 @@
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&sata {
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status = "okay";
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};
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+
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+&qspi {
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+ status = "okay";
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+ qflash0: s25fs512s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <0>;
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+ spi-rx-bus-width = <2>;
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+ spi-tx-bus-width = <2>;
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+ };
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+
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+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
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@@ -13,6 +13,11 @@
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model = "LS1012A QDS Board";
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compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+
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sys_mclk: clock-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -57,6 +62,10 @@
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};
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};
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+&pcie {
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+ status = "okay";
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+};
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+
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&dspi {
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bus-num = <0>;
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status = "okay";
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@@ -128,6 +137,44 @@
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};
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};
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x2>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x3>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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&sai2 {
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status = "okay";
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};
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@@ -135,3 +182,18 @@
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&sata {
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status = "okay";
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};
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+
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+&qspi {
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+ status = "okay";
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+ qflash0: s25fs512s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <0>;
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+ spi-rx-bus-width = <2>;
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+ spi-tx-bus-width = <2>;
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+ };
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+
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+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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@@ -12,6 +12,15 @@
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/ {
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model = "LS1012A RDB Board";
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compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
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+
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+};
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+
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+&pcie {
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+ status = "okay";
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};
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&duart0 {
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@@ -38,3 +47,56 @@
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&sata {
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status = "okay";
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};
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+
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
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+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "rgmii-txid";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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+&qspi {
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+ status = "okay";
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+ qflash0: s25fs512s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <0>;
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+ spi-rx-bus-width = <2>;
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+ spi-tx-bus-width = <2>;
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+ };
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+
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+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
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@@ -260,7 +260,7 @@
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1012a-dcfg",
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"syscon";
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- reg = <0x0 0x1ee0000 0x0 0x10000>;
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+ reg = <0x0 0x1ee0000 0x0 0x1000>;
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big-endian;
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};
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@@ -317,13 +317,23 @@
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#thermal-sensor-cells = <1>;
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};
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+ ftm0: ftm0@29d0000 {
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+ compatible = "fsl,ftm-alarm";
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+ reg = <0x0 0x29d0000 0x0 0x10000>,
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+ <0x0 0x1ee2140 0x0 0x4>;
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+ reg-names = "ftm", "FlexTimer1";
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+ interrupts = <0 86 0x4>;
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+ big-endian;
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+ };
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+
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i2c0: i2c@2180000 {
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- compatible = "fsl,vf610-i2c";
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+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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+ scl-gpios = <&gpio0 13 0>;
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status = "disabled";
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};
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@@ -395,6 +405,20 @@
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big-endian;
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};
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+ qspi: spi@1550000 {
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+ compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x1550000 0x0 0x10000>,
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+ <0x0 0x40000000 0x0 0x10000000>;
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+ reg-names = "QuadSPI", "QuadSPI-memory";
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+ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-names = "qspi_en", "qspi";
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+ clocks = <&clockgen 4 0>, <&clockgen 4 0>;
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+ big-endian;
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+ status = "disabled";
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+ };
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+
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sai1: sai@2b50000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,vf610-sai";
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@@ -499,6 +523,46 @@
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<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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+
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+ rcpm: rcpm@1ee2000 {
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+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
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+ reg = <0x0 0x1ee2000 0x0 0x1000>;
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+ fsl,#rcpm-wakeup-cells = <1>;
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+ };
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ pfe_reserved: packetbuffer@83400000 {
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+ reg = <0 0x83400000 0 0xc00000>;
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+ };
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+ };
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+
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+ pfe: pfe@04000000 {
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+ compatible = "fsl,pfe";
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+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
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+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
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+ reg-names = "pfe", "pfe-ddr";
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+ fsl,pfe-num-interfaces = <0x2>;
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+ interrupts = <0 172 0x4>, /* HIF interrupt */
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+ <0 173 0x4>, /*HIF_NOCPY interrupt */
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+ <0 174 0x4>; /* WoL interrupt */
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+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
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+ memory-region = <&pfe_reserved>;
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+ fsl,pfe-scfg = <&scfg 0>;
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+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
|
|
+ clocks = <&clockgen 4 0>;
|
|
+ clock-names = "pfe";
|
|
+
|
|
+ status = "okay";
|
|
+ pfe_mac0: ethernet@0 {
|
|
+ };
|
|
+
|
|
+ pfe_mac1: ethernet@1 {
|
|
+ };
|
|
};
|
|
|
|
firmware {
|