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72 lines
2.0 KiB
Diff
72 lines
2.0 KiB
Diff
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -587,6 +587,9 @@
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#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
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#define TIMER_CTL_ENABLE_MASK (1 << 31)
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+/* Clock reset control (63268 only) */
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+#define TIMER_CLK_RST_CTL_REG 0x2c
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+#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18)
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/*************************************************************************
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* _REG relative to RSET_WDT
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@@ -1534,6 +1537,11 @@
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#define STRAPBUS_63268_FCVO_SHIFT 21
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#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
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+#define MISC_IDDQ_CTRL_6328_REG 0x48
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+#define MISC_IDDQ_CTRL_63268_REG 0x4c
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+
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+#define IDDQ_CTRL_63268_USBH (1 << 4)
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+
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -64,6 +64,26 @@ static void bcm_ub_hwclock_set(u32 mask,
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bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
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}
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+static void bcm_misc_iddq_set(u32 mask, int enable)
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+{
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+ u32 offset;
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+ u32 reg;
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+
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
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+ offset = MISC_IDDQ_CTRL_6328_REG;
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+ else if (BCMCPU_IS_63268())
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+ offset = MISC_IDDQ_CTRL_63268_REG;
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+ else
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+ return;
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+
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+ reg = bcm_misc_readl(offset);
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+ if (enable)
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+ reg &= ~mask;
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+ else
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+ reg |= mask;
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+ bcm_misc_writel(reg, offset);
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+}
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+
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/*
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* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
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*/
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@@ -236,7 +256,17 @@ static void usbh_set(struct clk *clk, in
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} else if (BCMCPU_IS_6368()) {
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bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
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} else if (BCMCPU_IS_63268()) {
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+ u32 reg;
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+
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bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
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+ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
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+ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);
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+ if (enable)
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+ reg |= CLK_RST_CTL_USB_REF_CLK_EN;
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+ else
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+ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN;
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+ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);
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} else {
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return;
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}
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