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334 lines
11 KiB
Diff
334 lines
11 KiB
Diff
From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 15 Dec 2013 20:47:34 +0100
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Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318
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---
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arch/mips/bcm63xx/clk.c | 25 ++++-
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 ++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 60 +++++++++++-
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arch/mips/pci/ops-bcm63xx.c | 16 +++-
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arch/mips/pci/pci-bcm63xx.c | 106 ++++++++++++++++++----
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5 files changed, 184 insertions(+), 29 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -52,6 +52,18 @@ static void bcm_hwclock_set(u32 mask, in
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bcm_perf_writel(reg, PERF_CKCTL_REG);
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}
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+static void bcm_ub_hwclock_set(u32 mask, int enable)
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+{
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+ u32 reg;
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+
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+ reg = bcm_perf_readl(PERF_UB_CKCTL_REG);
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+ if (enable)
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+ reg |= mask;
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+ else
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+ reg &= ~mask;
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+ bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
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+}
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+
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/*
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* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
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*/
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@@ -362,12 +374,17 @@ static struct clk clk_ipsec = {
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static void pcie_set(struct clk *clk, int enable)
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{
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- if (BCMCPU_IS_6328())
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+ if (BCMCPU_IS_6318()) {
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+ bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable);
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+ bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable);
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+ bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable);
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+ } else if (BCMCPU_IS_6328()) {
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bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
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- else if (BCMCPU_IS_6362())
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+ } else if (BCMCPU_IS_6362()) {
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bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
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- else if (BCMCPU_IS_63268())
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+ } else if (BCMCPU_IS_63268()) {
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bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
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+ }
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}
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static struct clk clk_pcie = {
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -41,6 +41,12 @@
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#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
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BCM_CB_MEM_SIZE - 1)
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+#define BCM_PCIE_MEM_BASE_PA_6318 0x10200000
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+#define BCM_PCIE_MEM_SIZE_6318 (1 * 1024 * 1024)
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+#define BCM_PCIE_MEM_END_PA_6318 (BCM_PCIE_MEM_BASE_PA_6318 + \
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+ BCM_PCIE_MEM_SIZE_6318 - 1)
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+
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+
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#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000
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#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024)
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#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1530,6 +1530,17 @@
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* _REG relative to RSET_PCIE
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*************************************************************************/
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+#define PCIE_SPECIFIC_REG 0x188
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+#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0
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+#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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+#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2
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+#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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+#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4
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+#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
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+#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0
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+#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
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+#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2
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+
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#define PCIE_CONFIG2_REG 0x408
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#define CONFIG2_BAR1_SIZE_EN 1
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#define CONFIG2_BAR1_SIZE_MASK 0xf
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@@ -1575,7 +1586,54 @@
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#define PCIE_RC_INT_C (1 << 2)
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#define PCIE_RC_INT_D (1 << 3)
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-#define PCIE_DEVICE_OFFSET 0x8000
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+#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c
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+#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3
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+#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0
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+#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
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+#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
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+#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20
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+#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
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+
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+#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c
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+#define RC_BAR_CFG_LO_SIZE_256MB 0xd
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+#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20
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+#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
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+
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+#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
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+#define C2P_BASELIMIT_LIMIT_SHIFT 20
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+#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
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+#define C2P_BASELIMIT_BASE_SHIFT 4
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+#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT)
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+
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+#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088
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+#define BAR1_CFG_REMAP_OFFSET_SHIFT 20
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+#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
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+#define BAR1_CFG_REMAP_ACCESS_EN 1
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+
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+#define PCIE_HARD_DEBUG_REG 0x4204
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+#define HARD_DEBUG_SERDES_IDDQ (1 << 23)
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+
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+#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c
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+#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0)
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+#define CPU_INT_PCIE_INTA (1 << 1)
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+#define CPU_INT_PCIE_INTB (1 << 2)
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+#define CPU_INT_PCIE_INTC (1 << 3)
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+#define CPU_INT_PCIE_INTD (1 << 4)
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+#define CPU_INT_PCIE_INTR (1 << 5)
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+#define CPU_INT_PCIE_NMI (1 << 6)
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+#define CPU_INT_PCIE_UBUS (1 << 7)
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+#define CPU_INT_IPI (1 << 8)
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+
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+#define PCIE_EXT_CFG_INDEX_REG 0x8400
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+#define EXT_CFG_FUNC_NUM_SHIFT 12
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+#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT)
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+#define EXT_CFG_DEV_NUM_SHIFT 15
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+#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT)
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+#define EXT_CFG_BUS_NUM_SHIFT 20
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+#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT)
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+
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+#define PCIE_DEVICE_OFFSET_6318 0x9000
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+#define PCIE_DEVICE_OFFSET_6328 0x8000
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/*************************************************************************
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* _REG relative to RSET_OTP
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--- a/arch/mips/pci/ops-bcm63xx.c
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+++ b/arch/mips/pci/ops-bcm63xx.c
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@@ -489,8 +489,12 @@ static int bcm63xx_pcie_read(struct pci_
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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- if (bus->number == PCIE_BUS_DEVICE)
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- reg += PCIE_DEVICE_OFFSET;
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+ if (bus->number == PCIE_BUS_DEVICE) {
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+ if (BCMCPU_IS_6318())
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+ reg += PCIE_DEVICE_OFFSET_6318;
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+ else
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+ reg += PCIE_DEVICE_OFFSET_6328;
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+ }
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data = bcm_pcie_readl(reg);
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@@ -509,8 +513,12 @@ static int bcm63xx_pcie_write(struct pci
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if (!bcm63xx_pcie_can_access(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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- if (bus->number == PCIE_BUS_DEVICE)
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- reg += PCIE_DEVICE_OFFSET;
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+ if (bus->number == PCIE_BUS_DEVICE) {
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+ if (BCMCPU_IS_6318())
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+ reg += PCIE_DEVICE_OFFSET_6318;
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+ else
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+ reg += PCIE_DEVICE_OFFSET_6328;
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+ }
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data = bcm_pcie_readl(reg);
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v
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void __iomem *pci_iospace_start;
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-static void __init bcm63xx_reset_pcie(void)
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+static void __init bcm63xx_reset_pcie_gen1(void)
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{
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u32 val;
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u32 reg;
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@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo
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mdelay(200);
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}
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-static struct clk *pcie_clk;
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-
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-static int __init bcm63xx_register_pcie(void)
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+static void __init bcm63xx_reset_pcie_gen2(void)
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{
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u32 val;
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- /* enable clock */
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- pcie_clk = clk_get(NULL, "pcie");
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- if (IS_ERR_OR_NULL(pcie_clk))
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- return -ENODEV;
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
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- clk_prepare_enable(pcie_clk);
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+ /* reset the PCIe core */
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
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+ mdelay(10);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
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+ mdelay(10);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
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+ mdelay(10);
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+ val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG);
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+ val &= ~HARD_DEBUG_SERDES_IDDQ;
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+ bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG);
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+ mdelay(10);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
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+ mdelay(200);
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+}
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- bcm63xx_reset_pcie();
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+static void __init bcm63xx_init_pcie_gen1(void)
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+{
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+ u32 val;
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/* configure the PCIe bridge */
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val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
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@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie(
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val |= OPT2_CFG_TYPE1_BD_SEL;
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bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
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+ /* set bar0 to little endian */
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+ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
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+ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
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+ val |= BASEMASK_REMAP_EN;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
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+
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+ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
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+}
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+
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+static void __init bcm63xx_init_pcie_gen2(void)
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+{
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+ u32 val;
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+
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+ bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
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+ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
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+ PCIE_CPU_INT1_MASK_CLEAR_REG);
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+
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+ val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
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+ val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) <<
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+ C2P_BASELIMIT_BASE_SHIFT;
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+
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+ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
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+
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+ /* set bar0 to little endian */
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+ val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
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+ val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
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+ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
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+ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
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+
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+ bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG);
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+ bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG);
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+ bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG);
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+
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+ bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
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+ PCIE_EXT_CFG_INDEX_REG);
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+}
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+
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+static struct clk *pcie_clk;
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+
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+static int __init bcm63xx_register_pcie(void)
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+{
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+ u32 val;
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+
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+ /* enable clock */
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+ pcie_clk = clk_get(NULL, "pcie");
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+ if (IS_ERR_OR_NULL(pcie_clk))
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+ return -ENODEV;
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+
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+ clk_prepare_enable(pcie_clk);
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+
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
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+ bcm63xx_reset_pcie_gen1();
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+ bcm63xx_init_pcie_gen1();
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+ } else {
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+ bcm63xx_reset_pcie_gen2();
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+ bcm63xx_init_pcie_gen2();
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+ }
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+
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/* setup class code as bridge */
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val = bcm_pcie_readl(PCIE_IDVAL3_REG);
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val &= ~IDVAL3_CLASS_CODE_MASK;
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@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie(
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val &= ~CONFIG2_BAR1_SIZE_MASK;
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bcm_pcie_writel(val, PCIE_CONFIG2_REG);
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- /* set bar0 to little endian */
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- val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
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- val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
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- val |= BASEMASK_REMAP_EN;
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- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
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-
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- val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
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- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
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-
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register_pci_controller(&bcm63xx_pcie_controller);
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return 0;
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@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void)
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if (!bcm63xx_pci_enabled)
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return -ENODEV;
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- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
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+ if (BCMCPU_IS_6318()) {
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+ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318;
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+ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318;
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+ } if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
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bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
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bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
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} else if (BCMCPU_IS_63268()) {
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@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void)
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}
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switch (bcm63xx_get_cpu_id()) {
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+ case BCM6318_CPU_ID:
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case BCM6328_CPU_ID:
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case BCM6362_CPU_ID:
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case BCM63268_CPU_ID:
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