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195 lines
6.5 KiB
Diff
195 lines
6.5 KiB
Diff
From 7e7c7df5d50fe06469be106967fc5b5d62be8868 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Fri, 22 May 2020 14:15:24 +0200
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Subject: [PATCH] mtd: rawnand: brcmnand: support v2.1-v2.2 controllers
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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v2.1: tested on Netgear DGND3700v1 (BCM6368)
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v2.2: tested on Netgear DGND3700v2 (BCM6362)
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 85 +++++++++++++++++++++---
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1 file changed, 76 insertions(+), 9 deletions(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -196,6 +196,7 @@ struct brcmnand_controller {
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const unsigned int *block_sizes;
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unsigned int max_page_size;
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const unsigned int *page_sizes;
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+ unsigned int page_size_shift;
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unsigned int max_oob;
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u32 features;
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@@ -269,6 +270,36 @@ enum brcmnand_reg {
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BRCMNAND_FC_BASE,
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};
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+/* BRCMNAND v2.1-v2.2 */
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+static const u16 brcmnand_regs_v21[] = {
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+ [BRCMNAND_CMD_START] = 0x04,
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+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
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+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
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+ [BRCMNAND_INTFC_STATUS] = 0x5c,
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+ [BRCMNAND_CS_SELECT] = 0x14,
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+ [BRCMNAND_CS_XOR] = 0x18,
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+ [BRCMNAND_LL_OP] = 0,
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+ [BRCMNAND_CS0_BASE] = 0x40,
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+ [BRCMNAND_CS1_BASE] = 0,
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+ [BRCMNAND_CORR_THRESHOLD] = 0,
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+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
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+ [BRCMNAND_UNCORR_COUNT] = 0,
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+ [BRCMNAND_CORR_COUNT] = 0,
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+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
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+ [BRCMNAND_CORR_ADDR] = 0x64,
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+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
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+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
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+ [BRCMNAND_SEMAPHORE] = 0x50,
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+ [BRCMNAND_ID] = 0x54,
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+ [BRCMNAND_ID_EXT] = 0,
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+ [BRCMNAND_LL_RDATA] = 0,
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+ [BRCMNAND_OOB_READ_BASE] = 0x20,
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+ [BRCMNAND_OOB_READ_10_BASE] = 0,
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+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
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+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
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+ [BRCMNAND_FC_BASE] = 0x200,
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+};
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+
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/* BRCMNAND v3.3-v4.0 */
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static const u16 brcmnand_regs_v33[] = {
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[BRCMNAND_CMD_START] = 0x04,
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@@ -467,6 +498,9 @@ enum {
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CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
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CFG_DEVICE_SIZE_SHIFT = 24,
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+ /* Only for v2.1 */
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+ CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
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+
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/* Only for pre-v7.1 (with no CFG_EXT register) */
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CFG_PAGE_SIZE_SHIFT = 20,
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CFG_BLK_SIZE_SHIFT = 28,
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@@ -502,12 +536,16 @@ static int brcmnand_revision_init(struct
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{
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static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
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static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
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+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
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+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
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static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
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+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
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+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
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ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
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- /* Only support v4.0+? */
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- if (ctrl->nand_version < 0x0400) {
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+ /* Only support v2.1+ */
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+ if (ctrl->nand_version < 0x0201) {
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dev_err(ctrl->dev, "version %#x not supported\n",
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ctrl->nand_version);
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return -ENODEV;
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@@ -524,6 +562,8 @@ static int brcmnand_revision_init(struct
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ctrl->reg_offsets = brcmnand_regs_v50;
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else if (ctrl->nand_version >= 0x0303)
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ctrl->reg_offsets = brcmnand_regs_v33;
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+ else if (ctrl->nand_version >= 0x0201)
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+ ctrl->reg_offsets = brcmnand_regs_v21;
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/* Chip-select stride */
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if (ctrl->nand_version >= 0x0701)
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@@ -549,14 +589,32 @@ static int brcmnand_revision_init(struct
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ctrl->max_page_size = 16 * 1024;
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ctrl->max_block_size = 2 * 1024 * 1024;
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} else {
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- ctrl->page_sizes = page_sizes_v3_4;
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+ if (ctrl->nand_version >= 0x0304)
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+ ctrl->page_sizes = page_sizes_v3_4;
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+ else if (ctrl->nand_version >= 0x0202)
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+ ctrl->page_sizes = page_sizes_v2_2;
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+ else
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+ ctrl->page_sizes = page_sizes_v2_1;
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+
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+ if (ctrl->nand_version >= 0x0202)
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+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
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+ else
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+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
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+
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if (ctrl->nand_version >= 0x0600)
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ctrl->block_sizes = block_sizes_v6;
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- else
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+ else if (ctrl->nand_version >= 0x0400)
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ctrl->block_sizes = block_sizes_v4;
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+ else if (ctrl->nand_version >= 0x0202)
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+ ctrl->block_sizes = block_sizes_v2_2;
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+ else
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+ ctrl->block_sizes = block_sizes_v2_1;
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if (ctrl->nand_version < 0x0400) {
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- ctrl->max_page_size = 4096;
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+ if (ctrl->nand_version < 0x0202)
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+ ctrl->max_page_size = 2048;
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+ else
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+ ctrl->max_page_size = 4096;
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ctrl->max_block_size = 512 * 1024;
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}
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}
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@@ -724,6 +782,9 @@ static void brcmnand_wr_corr_thresh(stru
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enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
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int cs = host->cs;
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+ if (!ctrl->reg_offsets[reg])
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+ return;
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+
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if (ctrl->nand_version == 0x0702)
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bits = 7;
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else if (ctrl->nand_version >= 0x0600)
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@@ -782,8 +843,10 @@ static inline u32 brcmnand_spare_area_ma
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return GENMASK(7, 0);
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else if (ctrl->nand_version >= 0x0600)
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return GENMASK(6, 0);
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- else
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+ else if (ctrl->nand_version >= 0x0303)
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return GENMASK(5, 0);
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+ else
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+ return GENMASK(4, 0);
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}
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#define NAND_ACC_CONTROL_ECC_SHIFT 16
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@@ -2146,7 +2209,7 @@ static int brcmnand_set_cfg(struct brcmn
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(!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
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(device_size << CFG_DEVICE_SIZE_SHIFT);
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if (cfg_offs == cfg_ext_offs) {
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- tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
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+ tmp |= (page_size << ctrl->page_size_shift) |
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(block_size << CFG_BLK_SIZE_SHIFT);
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nand_writereg(ctrl, cfg_offs, tmp);
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} else {
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@@ -2158,9 +2221,11 @@ static int brcmnand_set_cfg(struct brcmn
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tmp = nand_readreg(ctrl, acc_control_offs);
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tmp &= ~brcmnand_ecc_level_mask(ctrl);
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- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
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tmp &= ~brcmnand_spare_area_mask(ctrl);
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- tmp |= cfg->spare_area_size;
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+ if (ctrl->nand_version >= 0x0302) {
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+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
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+ tmp |= cfg->spare_area_size;
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+ }
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nand_writereg(ctrl, acc_control_offs, tmp);
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brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
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@@ -2524,6 +2589,8 @@ const struct dev_pm_ops brcmnand_pm_ops
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EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
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static const struct of_device_id brcmnand_of_match[] = {
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+ { .compatible = "brcm,brcmnand-v2.1" },
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+ { .compatible = "brcm,brcmnand-v2.2" },
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{ .compatible = "brcm,brcmnand-v4.0" },
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{ .compatible = "brcm,brcmnand-v5.0" },
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{ .compatible = "brcm,brcmnand-v6.0" },
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