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91 lines
3.5 KiB
Diff
91 lines
3.5 KiB
Diff
From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Mon, 18 Mar 2019 00:54:06 +0100
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Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
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This adds missing GMAC register definitions for the Qualcomm Atheros
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QCA955X series MIPS SoCs.
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They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
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Repeater 450E's GPL tarball.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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.../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
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1 file changed, 54 insertions(+)
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1246,7 +1246,12 @@
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*/
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#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+#define QCA955X_GMAC_REG_SGMII_RESET 0x14
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#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
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+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
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+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
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+#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34
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+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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@@ -1268,9 +1273,58 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0
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+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
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+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
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+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
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+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
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+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
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+
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#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
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+
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+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6)
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+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8)
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+#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9)
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+#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11)
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+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
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+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13)
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+#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14)
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+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
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+
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+#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0)
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+#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2)
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+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
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+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4)
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+#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5)
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+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6)
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+#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7)
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+
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+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
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+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
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+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3)
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+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4)
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+#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5)
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+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6
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+#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0
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+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8)
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+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9)
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+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10)
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+#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11)
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+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12)
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+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13)
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+#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14)
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+
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+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff
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+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0
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+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00
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+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8
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+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000
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+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16
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+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000
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+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24
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+
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/*
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* QCA956X GMAC Interface
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*/
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