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330 lines
10 KiB
Diff
330 lines
10 KiB
Diff
--- a/drivers/net/tg3.c
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+++ b/drivers/net/tg3.c
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@@ -41,6 +41,7 @@
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#include <linux/prefetch.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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+#include <linux/ssb/ssb_driver_gige.h>
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#include <net/checksum.h>
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#include <net/ip.h>
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@@ -471,8 +472,9 @@ static void _tw32_flush(struct tg3 *tp,
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
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- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
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+ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
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+ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
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+ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
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tp->read32_mbox(tp, off);
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}
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@@ -482,7 +484,7 @@ static void tg3_write32_tx_mbox(struct t
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writel(val, mbox);
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if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
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writel(val, mbox);
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- if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
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+ if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
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readl(mbox);
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}
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@@ -783,7 +785,7 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
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+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
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{
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u32 frame_val;
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unsigned int loops;
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@@ -797,7 +799,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
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+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -832,7 +834,12 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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}
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-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
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+{
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+ return __tg3_readphy(tp, tp->phy_addr, reg, val);
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+}
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+
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+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
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{
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u32 frame_val;
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unsigned int loops;
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@@ -848,7 +855,7 @@ static int tg3_writephy(struct tg3 *tp,
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udelay(80);
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}
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- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
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+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -881,6 +888,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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}
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+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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+{
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+ return __tg3_writephy(tp, tp->phy_addr, reg, val);
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+}
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+
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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u32 phy_control;
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@@ -2389,6 +2401,9 @@ static int tg3_nvram_read(struct tg3 *tp
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{
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int ret;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
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+ return -ENODEV;
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+
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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@@ -2720,8 +2735,10 @@ static int tg3_set_power_state(struct tg
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tg3_frob_aux_power(tp);
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
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+ /* !!! FIXME !!! */
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -3214,6 +3231,14 @@ relink:
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tg3_phy_copper_begin(tp);
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+ if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
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+ current_link_up = 1;
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+ current_speed = SPEED_1000; /* FIXME */
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+ current_duplex = DUPLEX_FULL;
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+ tp->link_config.active_speed = current_speed;
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+ tp->link_config.active_duplex = current_duplex;
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+ }
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+
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tg3_readphy(tp, MII_BMSR, &tmp);
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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(tmp & BMSR_LSTATUS))
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@@ -6675,6 +6700,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* We don't use firmware. */
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+ return 0;
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+ }
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+
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -6958,6 +6988,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* BCM4785: In order to avoid repercussions from using potentially
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+ * defective internal ROM, stop the Rx RISC CPU, which is not
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+ * required. */
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+ tg3_stop_fw(tp);
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+ tg3_halt_cpu(tp, RX_CPU_BASE);
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+ }
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+
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -7135,9 +7173,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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}
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- /* Clear firmware's nvram arbitration. */
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- if (tp->tg3_flags & TG3_FLAG_NVRAM)
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- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
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+ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
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+ /* Clear firmware's nvram arbitration. */
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+ if (tp->tg3_flags & TG3_FLAG_NVRAM)
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+ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
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+ }
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+
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return 0;
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}
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@@ -7199,6 +7240,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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int err, i;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* We don't use firmware. */
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+ return 0;
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+ }
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+
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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@@ -7256,6 +7302,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* We don't use firmware. */
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+ return 0;
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+ }
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+
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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return 0;
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@@ -8380,6 +8431,11 @@ static void tg3_timer(unsigned long __op
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spin_lock(&tp->lock);
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+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
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+ /* BCM4785: Flush posted writes from GbE to host memory. */
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+ tr32(HOSTCC_MODE);
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+ }
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+
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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@@ -10279,6 +10335,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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return 0;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* We don't have NVRAM. */
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+ return 0;
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+ }
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+
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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@@ -11098,7 +11159,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
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+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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@@ -11114,7 +11175,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
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+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
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spin_unlock_bh(&tp->lock);
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return err;
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@@ -11759,6 +11820,12 @@ static void __devinit tg3_get_5717_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
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+ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
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+ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
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+ return;
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+ }
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+
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -12020,6 +12087,9 @@ static int tg3_nvram_write_block(struct
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{
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int ret;
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
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+ return -ENODEV;
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+
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -13360,6 +13430,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
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+ tp->write32_tx_mbox = tg3_write_flush_reg32;
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+ tp->write32_rx_mbox = tg3_write_flush_reg32;
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+ }
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+
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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@@ -13753,6 +13828,10 @@ static int __devinit tg3_get_device_addr
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
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+ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
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+ }
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+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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@@ -14272,6 +14351,7 @@ static char * __devinit tg3_phy_string(s
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case TG3_PHY_ID_BCM5704: return "5704";
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case TG3_PHY_ID_BCM5705: return "5705";
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case TG3_PHY_ID_BCM5750: return "5750";
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+ case TG3_PHY_ID_BCM5750_2: return "5750-2";
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case TG3_PHY_ID_BCM5752: return "5752";
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case TG3_PHY_ID_BCM5714: return "5714";
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case TG3_PHY_ID_BCM5780: return "5780";
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@@ -14481,6 +14561,13 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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+ if (pdev_is_ssb_gige_core(pdev)) {
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+ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
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+ if (ssb_gige_must_flush_posted_writes(pdev))
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+ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
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+ if (ssb_gige_have_roboswitch(pdev))
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+ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
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+ }
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/* The word/byte swap controls here control register access byte
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* swapping. DMA data byte swapping is controlled in the GRC_MODE
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--- a/drivers/net/tg3.h
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+++ b/drivers/net/tg3.h
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@@ -2014,6 +2014,9 @@
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#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
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#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
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#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
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+#define TG3_FLG3_IS_SSB_CORE 0x00000800
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+#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000
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+#define TG3_FLG3_ROBOSWITCH 0x00002000
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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@@ -2930,6 +2933,7 @@ struct tg3 {
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#define TG3_PHY_ID_BCM5704 0x60008190
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#define TG3_PHY_ID_BCM5705 0x600081a0
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#define TG3_PHY_ID_BCM5750 0x60008180
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+#define TG3_PHY_ID_BCM5750_2 0xbc050cd0
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#define TG3_PHY_ID_BCM5752 0x60008100
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#define TG3_PHY_ID_BCM5714 0x60008340
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#define TG3_PHY_ID_BCM5780 0x60008350
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@@ -2964,7 +2968,8 @@ struct tg3 {
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(X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
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(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
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(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
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- (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
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+ (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002 || \
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+ (X) == TG3_PHY_ID_BCM5750_2)
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u32 led_ctrl;
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u32 phy_otp;
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