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139 lines
5.2 KiB
Diff
139 lines
5.2 KiB
Diff
From b14de5c78d32f8f98535a99ea56bb924beb66810 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:31:29 +0200
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Subject: [PATCH 07/13] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
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second CPU
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Populate it for all platforms with a BMIPS4350.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 28 +++++++++++++++++++++++++++-
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1 file changed, 27 insertions(+), 1 deletion(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6328
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#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
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#define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
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+#define irq_stat_reg1 PERF_IRQSTAT_6328_REG(1)
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+#define irq_mask_reg1 PERF_IRQMASK_6328_REG(1)
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6338
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#define irq_stat_reg0 PERF_IRQSTAT_6338_REG
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#define irq_mask_reg0 PERF_IRQMASK_6338_REG
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+#define irq_stat_reg1 0
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+#define irq_mask_reg1 0
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#define irq_bits 32
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6345
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#define irq_stat_reg0 PERF_IRQSTAT_6345_REG
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#define irq_mask_reg0 PERF_IRQMASK_6345_REG
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+#define irq_stat_reg1 0
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+#define irq_mask_reg1 0
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#define irq_bits 32
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6348
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#define irq_stat_reg0 PERF_IRQSTAT_6348_REG
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#define irq_mask_reg0 PERF_IRQMASK_6348_REG
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+#define irq_stat_reg1 0
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+#define irq_mask_reg1 0
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#define irq_bits 32
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6358
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#define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
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#define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
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+#define irq_stat_reg1 PERF_IRQSTAT_6358_REG(1)
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+#define irq_mask_reg1 PERF_IRQMASK_6358_REG(1)
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#define irq_bits 32
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6362
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#define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
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#define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
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+#define irq_stat_reg1 PERF_IRQSTAT_6362_REG(1)
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+#define irq_mask_reg1 PERF_IRQMASK_6362_REG(1)
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
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#ifdef CONFIG_BCM63XX_CPU_6368
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#define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
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#define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
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+#define irq_stat_reg1 PERF_IRQSTAT_6368_REG(1)
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+#define irq_mask_reg1 PERF_IRQMASK_6368_REG(1)
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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@@ -117,13 +131,15 @@ static void __internal_irq_unmask_64(uns
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#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
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#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
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+#define irq_stat_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1)
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+#define irq_mask_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1)
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static inline void bcm63xx_init_irq(void)
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{
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}
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#else /* ! BCMCPU_RUNTIME_DETECT */
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-static u32 irq_stat_addr0, irq_mask_addr0;
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+static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
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static void (*dispatch_internal)(void);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_count;
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@@ -138,11 +154,15 @@ static void bcm63xx_init_irq(void)
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irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
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irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
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+ irq_stat_addr1 = bcm63xx_regset_address(RSET_PERF);
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+ irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
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irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
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+ irq_stat_addr1 += PERF_IRQSTAT_6328_REG(1);
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+ irq_stat_addr1 += PERF_IRQMASK_6328_REG(1);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -174,6 +194,8 @@ static void bcm63xx_init_irq(void)
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case BCM6358_CPU_ID:
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irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
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irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
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+ irq_stat_addr1 += PERF_IRQSTAT_6358_REG(1);
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+ irq_mask_addr1 += PERF_IRQMASK_6358_REG(1);
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irq_bits = 32;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -184,6 +206,8 @@ static void bcm63xx_init_irq(void)
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case BCM6362_CPU_ID:
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irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
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irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
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+ irq_stat_addr1 += PERF_IRQSTAT_6362_REG(1);
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+ irq_mask_addr1 += PERF_IRQMASK_6362_REG(1);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -194,6 +218,8 @@ static void bcm63xx_init_irq(void)
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case BCM6368_CPU_ID:
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irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
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irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
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+ irq_stat_addr1 += PERF_IRQSTAT_6368_REG(1);
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+ irq_mask_addr1 += PERF_IRQMASK_6368_REG(1);
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irq_bits = 64;
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ext_irq_count = 6;
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is_ext_irq_cascaded = 1;
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