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57 lines
1.7 KiB
Diff
57 lines
1.7 KiB
Diff
From 04ebfc3e25eaa3dd77544b4b950497990b1a327e Mon Sep 17 00:00:00 2001
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Date: Wed, 12 Jun 2019 20:24:53 +0200
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Subject: [PATCH] clk: bcm2835: remove pllb
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Commit 2256d89333bd17b8b56b42734a7e1046d52f7fc3 upstream.
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Raspberry Pi's firmware controls this pll, we should use the firmware
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interface to access it.
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Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Acked-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/bcm/clk-bcm2835.c | 30 ++++--------------------------
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1 file changed, 4 insertions(+), 26 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1755,32 +1755,10 @@ static const struct bcm2835_clk_desc clk
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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- /* PLLB is used for the ARM's clock. */
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- [BCM2835_PLLB] = REGISTER_PLL(
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- SOC_ALL,
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- .name = "pllb",
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- .cm_ctrl_reg = CM_PLLB,
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- .a2w_ctrl_reg = A2W_PLLB_CTRL,
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- .frac_reg = A2W_PLLB_FRAC,
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- .ana_reg_base = A2W_PLLB_ANA0,
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- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
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- .lock_mask = CM_LOCK_FLOCKB,
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-
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- .ana = &bcm2835_ana_default,
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-
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- .min_rate = 600000000u,
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- .max_rate = 3000000000u,
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- .max_fb_rate = BCM2835_MAX_FB_RATE),
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- [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
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- SOC_ALL,
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- .name = "pllb_arm",
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- .source_pll = "pllb",
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- .cm_reg = CM_PLLB,
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- .a2w_reg = A2W_PLLB_ARM,
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- .load_mask = CM_PLLB_LOADARM,
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- .hold_mask = CM_PLLB_HOLDARM,
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- .fixed_divider = 1,
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- .flags = CLK_SET_RATE_PARENT),
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+ /*
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+ * PLLB is used for the ARM's clock. Controlled by firmware, see
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+ * clk-raspberrypi.c.
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+ */
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/*
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* PLLC is the core PLL, used to drive the core VPU clock.
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