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206 lines
4.6 KiB
Diff
206 lines
4.6 KiB
Diff
From 5a054211d9380cef5a09da7c5e815c827f330a96 Mon Sep 17 00:00:00 2001
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From: Rohit Vaswani <rvaswani@codeaurora.org>
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Date: Fri, 1 Nov 2013 10:10:40 -0700
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Subject: [PATCH 021/182] ARM: dts: qcom: Add nodes necessary for SMP boot
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Add the necessary nodes to support SMP on MSM8660, MSM8960, and
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MSM8974/APQ8074. While we're here also add in the error
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interrupts for the Krait cache error detection.
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Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
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[sboyd: Split into separate patch, add error interrupts]
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-msm8660.dtsi | 24 ++++++++++++
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arch/arm/boot/dts/qcom-msm8960.dtsi | 52 ++++++++++++++++++++++++++
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arch/arm/boot/dts/qcom-msm8974.dtsi | 69 +++++++++++++++++++++++++++++++++++
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3 files changed, 145 insertions(+)
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--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
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@@ -9,6 +9,30 @@
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "qcom,scorpion";
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+ enable-method = "qcom,gcc-msm8660";
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ };
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+
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+ cpu@1 {
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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+ };
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+
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
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@@ -9,6 +9,36 @@
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compatible = "qcom,msm8960";
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interrupt-parent = <&intc>;
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupts = <1 14 0x304>;
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ qcom,saw = <&saw0>;
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+ };
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+
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+ cpu@1 {
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ qcom,saw = <&saw1>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ interrupts = <0 2 0x4>;
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+ };
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+ };
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+
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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@@ -53,6 +83,28 @@
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#reset-cells = <1>;
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};
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+ acc0: clock-controller@2088000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@2098000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ saw0: regulator@2089000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ saw1: regulator@2099000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
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@@ -9,6 +9,49 @@
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compatible = "qcom,msm8974";
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interrupt-parent = <&intc>;
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ interrupts = <1 9 0xf04>;
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v2";
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ };
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+
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+ cpu@1 {
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ };
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+
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+ cpu@2 {
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+ device_type = "cpu";
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+ reg = <2>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc2>;
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+ };
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+
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+ cpu@3 {
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+ device_type = "cpu";
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+ reg = <3>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc3>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ interrupts = <0 2 0x4>;
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+ qcom,saw = <&saw_l2>;
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+ };
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+ };
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+
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -91,6 +134,32 @@
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};
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};
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+ saw_l2: regulator@f9012000 {
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+ compatible = "qcom,saw2";
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+ reg = <0xf9012000 0x1000>;
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+ regulator;
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+ };
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+
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+ acc0: clock-controller@f9088000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@f9098000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
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+ };
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+
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+ acc2: clock-controller@f90a8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
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+ };
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+
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+ acc3: clock-controller@f90b8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
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+ };
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+
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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