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50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
From 3a4fe9a3a4aff8b1f1c3685bc9b6adbe739d7367 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Thu, 31 Oct 2013 18:20:30 -0700
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Subject: [PATCH 011/182] devicetree: bindings: Document qcom,kpss-acc
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The kpss acc binding describes the clock, reset, and power domain
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controller for a Krait CPU.
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Cc: <devicetree@vger.kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 30 ++++++++++++++++++++
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1 file changed, 30 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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@@ -0,0 +1,30 @@
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+Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
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+
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+The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
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+There is one ACC register region per CPU within the KPSS remapped region as
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+well as an alias register region that remaps accesses to the ACC associated
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+with the CPU accessing the region.
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+
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+PROPERTIES
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+
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+- compatible:
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+ Usage: required
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+ Value type: <string>
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+ Definition: should be one of:
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+ "qcom,kpss-acc-v1"
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+ "qcom,kpss-acc-v2"
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: the first element specifies the base address and size of
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+ the register region. An optional second element specifies
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+ the base address and size of the alias register region.
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+
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+Example:
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+
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+ clock-controller@2088000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0x02088000 0x1000>,
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+ <0x02008000 0x1000>;
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+ };
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