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301 lines
7.2 KiB
Diff
301 lines
7.2 KiB
Diff
From 3cdba35369b404875849008ea97cf1705e6060ed Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Thu, 23 Jan 2014 14:09:54 -0600
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Subject: [PATCH 001/182] ARM: dts: msm: split out msm8660 and msm8960 soc
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into dts include
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Pull the SoC device tree bits into their own files so other boards based
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on these SoCs can include them and reduce duplication across a number of
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boards.
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-msm8660-surf.dts | 59 +-------------------------
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arch/arm/boot/dts/qcom-msm8660.dtsi | 63 ++++++++++++++++++++++++++++
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arch/arm/boot/dts/qcom-msm8960-cdp.dts | 66 +----------------------------
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arch/arm/boot/dts/qcom-msm8960.dtsi | 70 +++++++++++++++++++++++++++++++
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4 files changed, 135 insertions(+), 123 deletions(-)
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create mode 100644 arch/arm/boot/dts/qcom-msm8660.dtsi
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create mode 100644 arch/arm/boot/dts/qcom-msm8960.dtsi
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--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
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+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
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@@ -1,63 +1,6 @@
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-/dts-v1/;
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-
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-/include/ "skeleton.dtsi"
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-
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-#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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+#include "qcom-msm8660.dtsi"
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/ {
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model = "Qualcomm MSM8660 SURF";
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compatible = "qcom,msm8660-surf", "qcom,msm8660";
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- interrupt-parent = <&intc>;
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-
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- intc: interrupt-controller@2080000 {
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- compatible = "qcom,msm-8660-qgic";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- reg = < 0x02080000 0x1000 >,
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- < 0x02081000 0x1000 >;
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- };
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-
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- timer@2000000 {
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- compatible = "qcom,scss-timer", "qcom,msm-timer";
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- interrupts = <1 0 0x301>,
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- <1 1 0x301>,
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- <1 2 0x301>;
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- reg = <0x02000000 0x100>;
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- clock-frequency = <27000000>,
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- <32768>;
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- cpu-offset = <0x40000>;
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- };
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-
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- msmgpio: gpio@800000 {
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- compatible = "qcom,msm-gpio";
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- reg = <0x00800000 0x4000>;
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- gpio-controller;
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- #gpio-cells = <2>;
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- ngpio = <173>;
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- interrupts = <0 16 0x4>;
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- interrupt-controller;
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- #interrupt-cells = <2>;
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- };
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-
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- gcc: clock-controller@900000 {
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- compatible = "qcom,gcc-msm8660";
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- reg = <0x900000 0x4000>;
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- };
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-
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- serial@19c40000 {
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- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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- reg = <0x19c40000 0x1000>,
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- <0x19c00000 0x1000>;
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- interrupts = <0 195 0x0>;
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- clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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- clock-names = "core", "iface";
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- };
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-
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- qcom,ssbi@500000 {
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- compatible = "qcom,ssbi";
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- reg = <0x500000 0x1000>;
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- qcom,controller-type = "pmic-arbiter";
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- };
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};
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
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@@ -0,0 +1,63 @@
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+/dts-v1/;
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+
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+/include/ "skeleton.dtsi"
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+
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+#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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+
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+/ {
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+ model = "Qualcomm MSM8660";
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+ compatible = "qcom,msm8660";
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+ interrupt-parent = <&intc>;
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+
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+ intc: interrupt-controller@2080000 {
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+ compatible = "qcom,msm-8660-qgic";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = < 0x02080000 0x1000 >,
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+ < 0x02081000 0x1000 >;
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+ };
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+
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+ timer@2000000 {
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+ compatible = "qcom,scss-timer", "qcom,msm-timer";
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+ interrupts = <1 0 0x301>,
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+ <1 1 0x301>,
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+ <1 2 0x301>;
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+ reg = <0x02000000 0x100>;
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+ clock-frequency = <27000000>,
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+ <32768>;
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+ cpu-offset = <0x40000>;
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+ };
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+
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+ msmgpio: gpio@800000 {
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+ compatible = "qcom,msm-gpio";
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+ reg = <0x00800000 0x4000>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ ngpio = <173>;
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+ interrupts = <0 16 0x4>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-msm8660";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ reg = <0x900000 0x4000>;
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+ };
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+
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+ serial@19c40000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x19c40000 0x1000>,
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+ <0x19c00000 0x1000>;
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+ interrupts = <0 195 0x0>;
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+ clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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+ clock-names = "core", "iface";
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+ };
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+
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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+};
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--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
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+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
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@@ -1,70 +1,6 @@
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-/dts-v1/;
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-
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-/include/ "skeleton.dtsi"
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-
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-#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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+#include "qcom-msm8960.dtsi"
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/ {
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model = "Qualcomm MSM8960 CDP";
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compatible = "qcom,msm8960-cdp", "qcom,msm8960";
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- interrupt-parent = <&intc>;
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-
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- intc: interrupt-controller@2000000 {
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- compatible = "qcom,msm-qgic2";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- reg = < 0x02000000 0x1000 >,
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- < 0x02002000 0x1000 >;
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- };
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-
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- timer@200a000 {
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- compatible = "qcom,kpss-timer", "qcom,msm-timer";
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- interrupts = <1 1 0x301>,
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- <1 2 0x301>,
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- <1 3 0x301>;
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- reg = <0x0200a000 0x100>;
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- clock-frequency = <27000000>,
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- <32768>;
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- cpu-offset = <0x80000>;
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- };
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-
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- msmgpio: gpio@800000 {
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- compatible = "qcom,msm-gpio";
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- gpio-controller;
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- #gpio-cells = <2>;
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- ngpio = <150>;
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- interrupts = <0 16 0x4>;
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- interrupt-controller;
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- #interrupt-cells = <2>;
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- reg = <0x800000 0x4000>;
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- };
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-
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- gcc: clock-controller@900000 {
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- compatible = "qcom,gcc-msm8960";
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- reg = <0x900000 0x4000>;
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- };
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-
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- clock-controller@4000000 {
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- compatible = "qcom,mmcc-msm8960";
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- reg = <0x4000000 0x1000>;
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- };
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-
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- serial@16440000 {
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- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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- reg = <0x16440000 0x1000>,
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- <0x16400000 0x1000>;
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- interrupts = <0 154 0x0>;
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- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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- clock-names = "core", "iface";
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- };
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-
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- qcom,ssbi@500000 {
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- compatible = "qcom,ssbi";
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- reg = <0x500000 0x1000>;
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- qcom,controller-type = "pmic-arbiter";
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- };
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};
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
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@@ -0,0 +1,70 @@
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+/dts-v1/;
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+
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+/include/ "skeleton.dtsi"
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+
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+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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+
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+/ {
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+ model = "Qualcomm MSM8960";
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+ compatible = "qcom,msm8960";
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+ interrupt-parent = <&intc>;
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+
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+ intc: interrupt-controller@2000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = < 0x02000000 0x1000 >,
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+ < 0x02002000 0x1000 >;
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+ };
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+
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+ timer@200a000 {
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+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
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+ interrupts = <1 1 0x301>,
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+ <1 2 0x301>,
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+ <1 3 0x301>;
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+ reg = <0x0200a000 0x100>;
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+ clock-frequency = <27000000>,
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+ <32768>;
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+ cpu-offset = <0x80000>;
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+ };
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+
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+ msmgpio: gpio@800000 {
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+ compatible = "qcom,msm-gpio";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ ngpio = <150>;
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+ interrupts = <0 16 0x4>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ reg = <0x800000 0x4000>;
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+ };
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+
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-msm8960";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ reg = <0x900000 0x4000>;
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+ };
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+
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+ clock-controller@4000000 {
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+ compatible = "qcom,mmcc-msm8960";
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+ reg = <0x4000000 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ serial@16440000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x16440000 0x1000>,
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+ <0x16400000 0x1000>;
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+ interrupts = <0 154 0x0>;
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+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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+ clock-names = "core", "iface";
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+ };
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+
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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+};
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