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287 lines
10 KiB
Diff
287 lines
10 KiB
Diff
From c3f16eeaa68f3be291dd62efadeb733d6d40279a Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Tue, 18 Feb 2020 09:13:00 +0800
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Subject: [PATCH] Revert "PCI: mobiveil: Fix csr_read()/write() build issue"
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This reverts commit 1865d6440fb63ad979d7034b2d7c94937bfd2200.
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PCI: mobiveil: Fix csr_read()/write() build issue
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[ Upstream commit 4906c05b87d44c19b225935e24d62e4480ca556d ]
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---
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drivers/pci/controller/pcie-mobiveil.c | 119 ++++++++++++++++-----------------
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1 file changed, 57 insertions(+), 62 deletions(-)
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--- a/drivers/pci/controller/pcie-mobiveil.c
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+++ b/drivers/pci/controller/pcie-mobiveil.c
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@@ -235,7 +235,7 @@ static int mobiveil_pcie_write(void __io
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return PCIBIOS_SUCCESSFUL;
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}
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-static u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
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+static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
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{
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void *addr;
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u32 val;
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@@ -250,8 +250,7 @@ static u32 mobiveil_csr_read(struct mobi
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return val;
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}
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-static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
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- size_t size)
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+static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
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{
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void *addr;
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int ret;
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@@ -263,19 +262,19 @@ static void mobiveil_csr_write(struct mo
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dev_err(&pcie->pdev->dev, "write CSR address failed\n");
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}
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-static u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
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+static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
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{
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- return mobiveil_csr_read(pcie, off, 0x4);
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+ return csr_read(pcie, off, 0x4);
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}
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-static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
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+static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
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{
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- mobiveil_csr_write(pcie, val, off, 0x4);
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+ csr_write(pcie, val, off, 0x4);
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}
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static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
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{
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- return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
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+ return (csr_readl(pcie, LTSSM_STATUS) &
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LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
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}
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@@ -324,7 +323,7 @@ static void __iomem *mobiveil_pcie_map_b
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
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- mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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+ csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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return pcie->config_axi_slave_base + where;
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}
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@@ -354,14 +353,13 @@ static void mobiveil_pcie_isr(struct irq
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chained_irq_enter(chip, desc);
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/* read INTx status */
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- val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
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- mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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+ val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
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+ mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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intr_status = val & mask;
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/* Handle INTx */
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if (intr_status & PAB_INTP_INTX_MASK) {
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- shifted_status = mobiveil_csr_readl(pcie,
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- PAB_INTP_AMBA_MISC_STAT);
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+ shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
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shifted_status &= PAB_INTP_INTX_MASK;
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shifted_status >>= PAB_INTX_START;
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do {
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@@ -375,13 +373,12 @@ static void mobiveil_pcie_isr(struct irq
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bit);
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/* clear interrupt handled */
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- mobiveil_csr_writel(pcie,
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- 1 << (PAB_INTX_START + bit),
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- PAB_INTP_AMBA_MISC_STAT);
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+ csr_writel(pcie, 1 << (PAB_INTX_START + bit),
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+ PAB_INTP_AMBA_MISC_STAT);
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}
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- shifted_status = mobiveil_csr_readl(pcie,
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- PAB_INTP_AMBA_MISC_STAT);
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+ shifted_status = csr_readl(pcie,
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+ PAB_INTP_AMBA_MISC_STAT);
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shifted_status &= PAB_INTP_INTX_MASK;
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shifted_status >>= PAB_INTX_START;
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} while (shifted_status != 0);
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@@ -416,7 +413,7 @@ static void mobiveil_pcie_isr(struct irq
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}
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/* Clear the interrupt status */
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- mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
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+ csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
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chained_irq_exit(chip, desc);
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}
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@@ -477,24 +474,24 @@ static void program_ib_windows(struct mo
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return;
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}
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- value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
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+ value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
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value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
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value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
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(lower_32_bits(size64) & WIN_SIZE_MASK);
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- mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
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+ csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(size64),
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- PAB_EXT_PEX_AMAP_SIZEN(win_num));
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+ csr_writel(pcie, upper_32_bits(size64),
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+ PAB_EXT_PEX_AMAP_SIZEN(win_num));
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- mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
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- PAB_PEX_AMAP_AXI_WIN(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
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- PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
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-
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- mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
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- PAB_PEX_AMAP_PEX_WIN_L(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
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- PAB_PEX_AMAP_PEX_WIN_H(win_num));
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+ csr_writel(pcie, lower_32_bits(cpu_addr),
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+ PAB_PEX_AMAP_AXI_WIN(win_num));
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+ csr_writel(pcie, upper_32_bits(cpu_addr),
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+ PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
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+
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+ csr_writel(pcie, lower_32_bits(pci_addr),
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+ PAB_PEX_AMAP_PEX_WIN_L(win_num));
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+ csr_writel(pcie, upper_32_bits(pci_addr),
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+ PAB_PEX_AMAP_PEX_WIN_H(win_num));
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pcie->ib_wins_configured++;
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}
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@@ -518,29 +515,27 @@ static void program_ob_windows(struct mo
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* program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
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* to 4 KB in PAB_AXI_AMAP_CTRL register
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*/
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- value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
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+ value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
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value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
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value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
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(lower_32_bits(size64) & WIN_SIZE_MASK);
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- mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
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+ csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(size64),
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- PAB_EXT_AXI_AMAP_SIZE(win_num));
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+ csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
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/*
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* program AXI window base with appropriate value in
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* PAB_AXI_AMAP_AXI_WIN0 register
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*/
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- mobiveil_csr_writel(pcie,
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- lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
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- PAB_AXI_AMAP_AXI_WIN(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
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- PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
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-
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- mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
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- PAB_AXI_AMAP_PEX_WIN_L(win_num));
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- mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
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- PAB_AXI_AMAP_PEX_WIN_H(win_num));
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+ csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
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+ PAB_AXI_AMAP_AXI_WIN(win_num));
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+ csr_writel(pcie, upper_32_bits(cpu_addr),
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+ PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
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+
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+ csr_writel(pcie, lower_32_bits(pci_addr),
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+ PAB_AXI_AMAP_PEX_WIN_L(win_num));
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+ csr_writel(pcie, upper_32_bits(pci_addr),
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+ PAB_AXI_AMAP_PEX_WIN_H(win_num));
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pcie->ob_wins_configured++;
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}
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@@ -584,42 +579,42 @@ static int mobiveil_host_init(struct mob
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struct resource_entry *win;
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/* setup bus numbers */
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- value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
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+ value = csr_readl(pcie, PCI_PRIMARY_BUS);
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value &= 0xff000000;
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value |= 0x00ff0100;
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- mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
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+ csr_writel(pcie, value, PCI_PRIMARY_BUS);
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/*
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* program Bus Master Enable Bit in Command Register in PAB Config
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* Space
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*/
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- value = mobiveil_csr_readl(pcie, PCI_COMMAND);
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+ value = csr_readl(pcie, PCI_COMMAND);
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value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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- mobiveil_csr_writel(pcie, value, PCI_COMMAND);
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+ csr_writel(pcie, value, PCI_COMMAND);
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/*
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* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
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* register
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*/
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- pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
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+ pab_ctrl = csr_readl(pcie, PAB_CTRL);
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pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
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- mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
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+ csr_writel(pcie, pab_ctrl, PAB_CTRL);
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- mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
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- PAB_INTP_AMBA_MISC_ENB);
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+ csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
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+ PAB_INTP_AMBA_MISC_ENB);
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/*
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* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
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* PAB_AXI_PIO_CTRL Register
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*/
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- value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
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+ value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
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value |= APIO_EN_MASK;
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- mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
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+ csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
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/* Enable PCIe PIO master */
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- value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
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+ value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
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value |= 1 << PIO_ENABLE_SHIFT;
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- mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
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+ csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
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/*
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* we'll program one outbound window for config reads and
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@@ -652,10 +647,10 @@ static int mobiveil_host_init(struct mob
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}
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/* fixup for PCIe class register */
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- value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
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+ value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
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value &= 0xff;
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value |= (PCI_CLASS_BRIDGE_PCI << 16);
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- mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
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+ csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
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/* setup MSI hardware registers */
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mobiveil_pcie_enable_msi(pcie);
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@@ -673,9 +668,9 @@ static void mobiveil_mask_intx_irq(struc
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pcie = irq_desc_get_chip_data(desc);
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mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
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raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
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- shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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+ shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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shifted_val &= ~mask;
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- mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
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+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
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raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
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}
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@@ -689,9 +684,9 @@ static void mobiveil_unmask_intx_irq(str
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pcie = irq_desc_get_chip_data(desc);
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mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
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raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
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- shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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+ shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
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shifted_val |= mask;
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- mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
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+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
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raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
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}
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