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88 lines
2.8 KiB
Diff
88 lines
2.8 KiB
Diff
From a10d0b8516bc3f48f0c1005f8e69efce12cea8f9 Mon Sep 17 00:00:00 2001
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From: Sandor Yu <Sandor.yu@nxp.com>
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Date: Mon, 23 Sep 2019 09:09:38 +0800
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Subject: [PATCH] drm: imx: hdmi: support arc function
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Add HDMI ARC configurate function.
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Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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---
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drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c | 59 +++++++++++++++++++++++++++++++++
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1 file changed, 59 insertions(+)
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--- a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
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+++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
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@@ -192,6 +192,62 @@ static const struct hdmi_pll_tuning imx8
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{ 7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680, 0x04F, 0, 0, 0 }
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};
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+static void hdmi_arc_config(struct cdns_mhdp_device *mhdp)
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+{
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+ u16 txpu_calib_code;
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+ u16 txpd_calib_code;
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+ u16 txpu_adj_calib_code;
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+ u16 txpd_adj_calib_code;
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+ u16 prev_calib_code;
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+ u16 new_calib_code;
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+ u16 rdata;
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+
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+ /* Power ARC */
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+ cdns_phy_reg_write(mhdp, TXDA_CYA_AUXDA_CYA, 0x0001);
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+
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+ prev_calib_code = cdns_phy_reg_read(mhdp, TX_DIG_CTRL_REG_2);
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+ txpu_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPUCAL_CTRL);
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+ txpd_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPDCAL_CTRL);
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+ txpu_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPU_ADJ_CTRL);
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+ txpd_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPD_ADJ_CTRL);
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+
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+ new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
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+ + txpu_adj_calib_code + txpd_adj_calib_code;
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+
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+ if (new_calib_code != prev_calib_code) {
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+ rdata = cdns_phy_reg_read(mhdp, TX_ANA_CTRL_REG_1);
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+ rdata &= 0xDFFF;
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
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+ cdns_phy_reg_write(mhdp, TX_DIG_CTRL_REG_2, new_calib_code);
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+ mdelay(10);
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+ rdata |= 0x2000;
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
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+ udelay(150);
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+ }
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+
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0100);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0300);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_3, 0x0000);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2008);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2018);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2098);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030C);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_5, 0x0010);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_4, 0x4001);
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+ mdelay(5);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2198);
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+ mdelay(5);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030D);
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+ udelay(100);
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+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030F);
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+}
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+
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static void hdmi_phy_set_vswing(struct cdns_mhdp_device *mhdp)
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{
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const u32 num_lanes = 4;
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@@ -604,6 +660,9 @@ static int hdmi_phy_power_up(struct cdns
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return -1;
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}
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+ /* Power up ARC */
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+ hdmi_arc_config(mhdp);
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+
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/* Configure PHY in A0 mode (PHY must be in the A0 power
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* state in order to transmit data)
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*/
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