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248 lines
5.6 KiB
Diff
248 lines
5.6 KiB
Diff
From c9be87f17c64d08c06e4858589a0014f73868867 Mon Sep 17 00:00:00 2001
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From: Pankaj Bansal <pankaj.bansal@nxp.com>
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Date: Thu, 28 Feb 2019 17:28:36 +0530
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Subject: [PATCH] arm64: dts: lx2160aqds: Add mdio mux nodes
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The two external MDIO buses used to communicate with phy devices that are
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external to SOC are muxed in LX2160AQDS board.
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These buses can be routed to any one of the eight IO slots on LX2160AQDS
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board depending on value in fpga register 0x54.
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Additionally the external MDIO1 is used to communicate to the onboard
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RGMII phy devices.
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The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is
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controlled by bits 4-7 of fpga register.
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Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 8 ++
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arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++--
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3 files changed, 165 insertions(+), 12 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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@@ -29,6 +29,130 @@
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regulator-boot-on;
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regulator-always-on;
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};
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+
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+ mdio-mux-1 {
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+ compatible = "mdio-mux-multiplexer";
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+ mux-controls = <&mux 0>;
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+ mdio-parent-bus = <&emdio1>;
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+ #address-cells=<1>;
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+ #size-cells = <0>;
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+
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+ mdio@0 { /* On-board PHY #1 RGMI1*/
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+ reg = <0x00>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@8 { /* On-board PHY #2 RGMI2*/
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+ reg = <0x8>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@18 { /* Slot #1 */
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+ reg = <0x18>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@19 { /* Slot #2 */
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+ reg = <0x19>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1a { /* Slot #3 */
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+ reg = <0x1a>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1b { /* Slot #4 */
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+ reg = <0x1b>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1c { /* Slot #5 */
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+ reg = <0x1c>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1d { /* Slot #6 */
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+ reg = <0x1d>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1e { /* Slot #7 */
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+ reg = <0x1e>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1f { /* Slot #8 */
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+ reg = <0x1f>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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+ mdio-mux-2 {
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+ compatible = "mdio-mux-multiplexer";
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+ mux-controls = <&mux 1>;
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+ mdio-parent-bus = <&emdio2>;
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+ #address-cells=<1>;
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+ #size-cells = <0>;
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+
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+ mdio@0 { /* Slot #1 (secondary EMI) */
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+ reg = <0x00>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@1 { /* Slot #2 (secondary EMI) */
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+ reg = <0x01>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@2 { /* Slot #3 (secondary EMI) */
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+ reg = <0x02>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@3 { /* Slot #4 (secondary EMI) */
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+ reg = <0x03>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@4 { /* Slot #5 (secondary EMI) */
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+ reg = <0x04>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@5 { /* Slot #6 (secondary EMI) */
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+ reg = <0x05>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@6 { /* Slot #7 (secondary EMI) */
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+ reg = <0x06>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mdio@7 { /* Slot #8 (secondary EMI) */
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+ reg = <0x07>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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};
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&crypto {
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@@ -71,6 +195,14 @@
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};
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};
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+&emdio1 {
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+ status = "okay";
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+};
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+
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+&emdio2 {
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+ status = "okay";
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+};
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+
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&esdhc0 {
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status = "okay";
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};
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@@ -82,6 +214,19 @@
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&i2c0 {
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status = "okay";
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+ fpga@66 {
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+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
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+ "simple-mfd";
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+ reg = <0x66>;
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+
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+ mux: mux-controller {
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+ compatible = "reg-mux";
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+ #mux-control-cells = <1>;
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+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
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+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
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+ };
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+ };
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+
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
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@@ -35,6 +35,14 @@
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status = "okay";
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};
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+&emdio1 {
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+ status = "okay";
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+};
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+
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+&emdio2 {
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+ status = "okay";
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+};
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+
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&esdhc0 {
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -478,26 +478,26 @@
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little-endian;
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};
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- /* TODO: WRIOP (CCSR?) */
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- emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
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+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
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+ emdio1: mdio@8b96000 {
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compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8B96000 0x0 0x1000>;
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- device_type = "mdio"; /* TODO: is this necessary? */
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- little-endian; /* force the driver in LE mode */
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-
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- /* Not necessary on the QDS, but needed on the RDB */
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+ reg = <0x0 0x8b96000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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+ little-endian; /* force the driver in LE mode */
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+ status = "disabled";
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};
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- emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
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+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
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+ emdio2: mdio@8b97000 {
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compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8B97000 0x0 0x1000>;
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- device_type = "mdio"; /* TODO: is this necessary? */
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- little-endian; /* force the driver in LE mode */
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-
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+ reg = <0x0 0x8b97000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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+ little-endian; /* force the driver in LE mode */
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+ status = "disabled";
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};
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pcs_mdio1: mdio@0x8c07000 {
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