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165 lines
3.5 KiB
Diff
165 lines
3.5 KiB
Diff
From 5508bc9764760ca32990d5f7fa494be78e711ff6 Mon Sep 17 00:00:00 2001
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From: Li Yang <leoyang.li@nxp.com>
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Date: Fri, 5 Oct 2018 18:22:46 -0500
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Subject: [PATCH] arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
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This patch add support for NXP LS2081ARDB board which has
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LS2081A SoC.
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LS2081A SoC is 40-pin derivative of LS2088A SoC
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So, from functional perspective both are same.
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Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
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Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
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Signed-off-by: Tao Yang <b31903@freescale.com>
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Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
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Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
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Signed-off-by: Li Yang <leoyang.li@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 127 ++++++++++++++++++++++
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2 files changed, 128 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
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@@ -0,0 +1,127 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree file for NXP LS2081A RDB Board.
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+ *
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+ * Copyright 2017 NXP
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+ *
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+ * Priyanka Jain <priyanka.jain@nxp.com>
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+ *
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+ */
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+
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+/dts-v1/;
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+
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+#include "fsl-ls2088a.dtsi"
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+
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+/ {
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+ model = "NXP Layerscape 2081A RDB Board";
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+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
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+
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+ aliases {
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+ serial0 = &serial0;
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+ serial1 = &serial1;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial1:115200n8";
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+ };
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+};
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+
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+&esdhc {
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+ status = "okay";
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+};
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+
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+&ifc {
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+ status = "disabled";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ pca9547@75 {
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+ compatible = "nxp,pca9547";
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+ reg = <0x75>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x01>;
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ };
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+ };
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+
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+ i2c@2 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x02>;
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+
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+ ina220@40 {
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+ compatible = "ti,ina220";
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+ reg = <0x40>;
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+ shunt-resistor = <500>;
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+ };
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+ };
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+
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ adt7481@4c {
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+ compatible = "adi,adt7461";
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+ reg = <0x4c>;
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+ };
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+ };
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+ };
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+};
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+
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+&dspi {
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+ status = "okay";
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+ dflash0: n25q512a@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <3000000>;
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+ reg = <0>;
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+ };
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+};
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+
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+&qspi {
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+ status = "okay";
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+ fsl,qspi-has-second-chip;
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+ flash0: s25fs512s@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spansion,m25p80";
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <4>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+ flash1: s25fs512s@1 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <4>;
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+ compatible = "spansion,m25p80";
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+ spi-max-frequency = <20000000>;
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+ reg = <1>;
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+ };
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&sata1 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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