--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -220,4 +220,9 @@ config VMD
 	  To compile this driver as a module, choose M here: the
 	  module will be called vmd.
 
+config PCIE_OXNAS
+	bool "PLX Oxnas PCIe controller"
+	depends on ARCH_OXNAS
+	select PCIEPORTBUS
+
 endmenu
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 
--- a/arch/arm/boot/dts/ox820.dtsi
+++ b/arch/arm/boot/dts/ox820.dtsi
@@ -302,6 +302,83 @@
 				reg = <0x1000 0x1000>,
 				      <0x100 0x500>;
 			};
+
+			pcie0: pcie-controller@c00000 {
+				compatible = "plxtech,nas782x-pcie";
+				device_type = "pci";
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				/*		flag & space	bus address	host address	size */
+				ranges = <	0x82000000	0 0x48000000	0x48000000	0 0x2000000
+						0xC2000000	0 0x4A000000	0x4A000000	0 0x1E00000
+						0x81000000	0 0x4BE00000	0x4BE00000	0 0x0100000
+						0x80000000	0 0x4BF00000	0x4BF00000	0 0x0100000>;
+
+				bus-range = <0x00 0x7f>;
+
+				/*	cfg			inbound translator	phy*/
+				reg =	<0x47C00000 0x1000>,	<0x47D00000 0x100>,	 <0x44A00000 0x10>;
+
+				#interrupt-cells = <1>;
+				/* wild card mask, match all bus address & interrupt specifier */
+				/* format: bus address mask, interrupt specifier mask */
+				/* each bit 1 means need match, 0 means ignored when match */
+				interrupt-map-mask = <0 0 0 0>;
+				/* format: a list of: bus address, interrupt specifier,
+				 * parent interrupt controller & specifier */
+				interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
+
+				gpios = <&gpio1 12 0>;
+				clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
+				clock-names = "pcie", "busclk";
+				resets = <&reset RESET_PCIEA>, <&reset RESET_PCIEPHY>;
+				reset-names = "pcie", "phy";
+
+				plxtech,pcie-hcsl-bit = <2>;
+				plxtech,pcie-ctrl-offset = <0x120>;
+				plxtech,pcie-outbound-offset = <0x138>;
+				status = "disabled";
+			};
+
+			pcie1: pcie-controller@e00000 {
+				compatible = "plxtech,nas782x-pcie";
+				device_type = "pci";
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				/*		flag & space	bus address	host address	size */
+				ranges = <	0x82000000	0 0x4C000000	0x4C000000	0 0x2000000
+						0xC2000000	0 0x4E000000	0x4E000000	0 0x1E00000
+						0x81000000	0 0x4FE00000	0x4FE00000	0 0x0100000
+						0x80000000	0 0x4FF00000	0x4FF00000	0 0x0100000>;
+
+				bus-range = <0x80 0xff>;
+
+				/*	cfg			inbound translator	phy*/
+				reg =	<0x47E00000 0x1000>,	<0x47F00000 0x100>,	<0x44A00000 0x10>;
+
+				#interrupt-cells = <1>;
+				/* wild card mask, match all bus address & interrupt specifier */
+				/* format: bus address mask, interrupt specifier mask */
+				/* each bit 1 means need match, 0 means ignored when match */
+				interrupt-map-mask = <0 0 0 0>;
+				/* format: a list of: bus address, interrupt specifier,
+				 * parent interrupt controller & specifier */
+				interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
+
+				/* gpios = <&gpio1 12 0>; */
+				clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
+				clock-names = "pcie", "busclk";
+				resets = <&reset RESET_PCIEB>, <&reset RESET_PCIEPHY>;
+				reset-names = "pcie", "phy";
+
+				plxtech,pcie-hcsl-bit = <3>;
+				plxtech,pcie-ctrl-offset = <0x124>;
+				plxtech,pcie-outbound-offset = <0x174>;
+				status = "disabled";
+			};
+
 		};
 	};
 };