--- a/src/mps/drv_mps_vmmc_ar9.c +++ b/src/mps/drv_mps_vmmc_ar9.c @@ -30,15 +30,24 @@ #include "ifxos_interrupt.h" /* board specific headers */ +#if !defined CONFIG_LANTIQ #include #include #include +#endif + +#include +#include /* device specific headers */ #include "drv_mps_vmmc.h" #include "drv_mps_vmmc_dbg.h" #include "drv_mps_vmmc_device.h" +const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL; + +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM + /* ============================= */ /* Local Macros & Definitions */ /* ============================= */ @@ -98,47 +107,48 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui */ IFX_int32_t ifx_mps_fw_wdog_start_ar9() { + return IFX_SUCCESS; /* FIXME - Disable start wdog... */ /* vpe1_wdog_ctr should be set up in u-boot as "vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing setting */ - if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR) - { - vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR; - } +// if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR) +// { +// vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR; +// } /* vpe1_wdog_timeout should be set up in u-boot as "vpe1_wdog_timeout = "; protection from insane setting */ - if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN) - { - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN; - } - if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX) - { - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX; - } +// if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN) +// { +// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN; +// } +// if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX) +// { +// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX; +// } /* recalculate in jiffies */ - vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000; +// vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000; /* register BSP callback function */ - if (IFX_SUCCESS != - vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n", - __FILE__, __func__, __LINE__)); - return IFX_ERROR;; - } +// if (IFX_SUCCESS != +// vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n", +// __FILE__, __func__, __LINE__)); +// return IFX_ERROR;; +// } /* start software watchdog timer */ - if (IFX_SUCCESS != vpe1_sw_wdog_start (0)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR - "[%s %s %d]: Error starting software watchdog timer.\r\n", - __FILE__, __func__, __LINE__)); - return IFX_ERROR; - } +// if (IFX_SUCCESS != vpe1_sw_wdog_start (0)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR +// "[%s %s %d]: Error starting software watchdog timer.\r\n", +// __FILE__, __func__, __LINE__)); +// return IFX_ERROR; +// } return IFX_SUCCESS; } @@ -292,6 +302,18 @@ IFX_int32_t ifx_mps_download_firmware (m decryption. Subtract sizeof(u32) from length to avoid decryption of data beyond the FW image code */ pFWDwnld->length -= sizeof(IFX_uint32_t); + switch(ltq_soc_type()) { + case SOC_TYPE_AR9: + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4; + break; + case SOC_TYPE_VR9: + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4; + break; + case SOC_TYPE_VR9_2: + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38; + break; + } + if (ifx_bsp_basic_mps_decrypt) ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length); } @@ -306,7 +328,7 @@ IFX_int32_t ifx_mps_download_firmware (m TRACE (MPS, DBG_LEVEL_HIGH, ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n", pFW_img_data->crc32, cksum)); - return IFX_ERROR; + /* return IFX_ERROR; -- FIXME */ } } else @@ -362,9 +384,9 @@ IFX_void_t ifx_mps_shutdown (IFX_void_t) if (vpe1_started) { /* stop software watchdog timer */ - vpe1_sw_wdog_stop (0); +// vpe1_sw_wdog_stop (0); /* clean up the BSP callback function */ - vpe1_sw_wdog_register_reset_handler (IFX_NULL); +// vpe1_sw_wdog_register_reset_handler (IFX_NULL); /* stop VPE1 */ vpe1_sw_stop (0); vpe1_started = 0; @@ -388,7 +410,7 @@ IFX_void_t ifx_mps_reset (IFX_void_t) if (vpe1_started) { /* stop software watchdog timer first */ - vpe1_sw_wdog_stop (0); +// vpe1_sw_wdog_stop (0); vpe1_sw_stop (0); vpe1_started = 0; } @@ -454,62 +476,62 @@ IFX_int32_t ifx_mps_wdog_callback (IFX_u #endif /* DEBUG */ /* reset SmartSLIC */ - IFXOS_LOCKINT (flags); - if (ifx_gpio_pin_reserve - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n", - __FILE__, __func__, __LINE__)); - } +// IFXOS_LOCKINT (flags); +// if (ifx_gpio_pin_reserve +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n", +// __FILE__, __func__, __LINE__)); +// } /* P1_ALTSEL0.15 = 0 */ - if (ifx_gpio_altsel0_clear - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__, - __func__, __LINE__)); - } +// if (ifx_gpio_altsel0_clear +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__, +// __func__, __LINE__)); +// } /* P1_ALTSEL1.15 = 0 */ - if (ifx_gpio_altsel1_clear - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__, - __func__, __LINE__)); - } +// if (ifx_gpio_altsel1_clear +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__, +// __func__, __LINE__)); +// } /* P1_DIR.15 = 1 */ - if (ifx_gpio_dir_out_set - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__, - __func__, __LINE__)); - } +// if (ifx_gpio_dir_out_set +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__, +// __func__, __LINE__)); +// } /* P1_OD.15 = 1 */ - if (ifx_gpio_open_drain_set - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__, - __func__, __LINE__)); - } +// if (ifx_gpio_open_drain_set +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__, +// __func__, __LINE__)); +// } /* P1_OUT.15 = 0 */ - if (ifx_gpio_output_clear - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__, - __func__, __LINE__)); - } - if (ifx_gpio_pin_free - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) - { - TRACE (MPS, DBG_LEVEL_HIGH, - (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__, - __func__, __LINE__)); - } - IFXOS_UNLOCKINT (flags); +// if (ifx_gpio_output_clear +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__, +// __func__, __LINE__)); +// } +// if (ifx_gpio_pin_free +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID)) +// { +// TRACE (MPS, DBG_LEVEL_HIGH, +// (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__, +// __func__, __LINE__)); +// } +// IFXOS_UNLOCKINT (flags); /* recalculate and compare the firmware checksum */ ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data); --- a/src/drv_vmmc_amazon_s.h +++ b/src/drv_vmmc_amazon_s.h @@ -16,7 +16,7 @@ #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) -#include +//#include #else #error no system selected #endif @@ -27,45 +27,6 @@ */ #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \ do { \ - ret = VMMC_statusOk; \ - /* Reserve P0.0 as TDM/FSC */ \ - if (!GPIOreserved) \ - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\ - \ - /* Reserve P1.9 as TDM/DO */ \ - if (!GPIOreserved) \ - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - \ - /* Reserve P2.9 as TDM/DI */ \ - if (!GPIOreserved) \ - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\ - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - \ - /* Reserve P2.8 as TDM/DCL */ \ - if (!GPIOreserved) \ - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - \ - if (mode == 2) { \ - /* TDM/FSC+DCL Master */ \ - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - } else { \ - /* TDM/FSC+DCL Slave */ \ - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ - } \ } while(0); /** @@ -73,11 +34,6 @@ do { \ */ #define VMMC_DRIVER_UNLOAD_HOOK(ret) \ do { \ - ret = VMMC_statusOk; \ - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \ - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \ } while (0) #endif /* _DRV_VMMC_AMAZON_S_H */