From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 2 Feb 2019 02:48:35 +0100 Subject: [PATCH] net: mdio: add ipq8064 mdio driver Signed-off-by: Christian Lamparter --- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/phy/mdio-ipq8064.c --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -156,6 +156,14 @@ config MDIO_I2C This is library mode. +config MDIO_IPQ8064 + tristate "Qualcomm IPQ8064 MDIO interface support" + depends on HAS_IOMEM && OF_MDIO + depends on MFD_SYSCON + help + This driver supports the MDIO interface found in the network + interface units of the IPQ8064 SoC + config MDIO_MOXART tristate "MOXA ART MDIO interface support" depends on ARCH_MOXART || COMPILE_TEST --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o +obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o --- /dev/null +++ b/drivers/net/phy/mdio-ipq8064.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Qualcomm IPQ8064 MDIO interface driver +// +// Copyright (C) 2019 Christian Lamparter + +#include +#include +#include +#include +#include +#include +#include +#include + +/* MII address register definitions */ +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE_60_100M (0 << 2) +#define MII_CLKRANGE_100_150M (1 << 2) +#define MII_CLKRANGE_20_35M (2 << 2) +#define MII_CLKRANGE_35_60M (3 << 2) +#define MII_CLKRANGE_150_250M (4 << 2) +#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_CLKRANGE_MASK GENMASK(4, 2) +#define MII_REG_SHIFT 6 +#define MII_REG_MASK GENMASK(10, 6) +#define MII_ADDR_SHIFT 11 +#define MII_ADDR_MASK GENMASK(15, 11) + +#define MII_DATA_REG_ADDR 0x14 + +#define MII_MDIO_DELAY (1000) +#define MII_MDIO_RETRY (10) + +struct ipq8064_mdio { + struct regmap *base; /* NSS_GMAC0_BASE */ +}; + +static int +ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) +{ + int i; + + for (i = 0; i < MII_MDIO_RETRY; i++) { + unsigned int busy; + + regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy); + if (!(busy & MII_BUSY)) + return 0; + + udelay(MII_MDIO_DELAY); + } + + return -ETIMEDOUT; +} + +static int +ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; + u32 ret_val; + int err; + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + udelay(10); + + err = ipq8064_mdio_wait_busy(priv); + if (err) + return err; + + regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); + return (int)ret_val; +} + +static int +ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; + + regmap_write(priv->base, MII_DATA_REG_ADDR, data); + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + udelay(10); + + return ipq8064_mdio_wait_busy(priv); +} + +static int +ipq8064_mdio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct ipq8064_mdio *priv; + struct mii_bus *bus; + int ret; + + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + bus->name = "ipq8064_mdio_bus"; + bus->read = ipq8064_mdio_read; + bus->write = ipq8064_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); + bus->parent = &pdev->dev; + + priv = bus->priv; + priv->base = syscon_node_to_regmap(np); + if (IS_ERR_OR_NULL(priv->base)) { + priv->base = syscon_regmap_lookup_by_phandle(np, "master"); + if (IS_ERR_OR_NULL(priv->base)) { + pr_err("master phandle not found\n"); + return -EINVAL; + } + } + + ret = of_mdiobus_register(bus, np); + if (ret) + return ret; + + platform_set_drvdata(pdev, bus); + return 0; +} + +static int +ipq8064_mdio_remove(struct platform_device *pdev) +{ + struct mii_bus *bus = platform_get_drvdata(pdev); + + mdiobus_unregister(bus); + + return 0; +} + +static const struct of_device_id ipq8064_mdio_dt_ids[] = { + { .compatible = "qcom,ipq8064-mdio" }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); + +static struct platform_driver ipq8064_mdio_driver = { + .probe = ipq8064_mdio_probe, + .remove = ipq8064_mdio_remove, + .driver = { + .name = "ipq8064-mdio", + .of_match_table = ipq8064_mdio_dt_ids, + }, +}; + +module_platform_driver(ipq8064_mdio_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); +MODULE_AUTHOR("Christian Lamparter "); +MODULE_LICENSE("GPL");