Commit Graph

10 Commits (dcb5e52209e52b6004b5888d41620386a28d2567)

Author SHA1 Message Date
Martin Blumenstingl dcb5e52209 lantiq: dts: assign the STP pins to the STP GPIO controller node
Assign the STP pins to the STP GPIO controller node instead of using
pin hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 years ago
Martin Blumenstingl 7298c25f74 lantiq: dts: assign the NAND pins to the nand-controller node
Assign the NAND pins to the NAND controller node instead of using pin
hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.

While here, define all NAND pins (CLE, ALE, read/RD, ready busy/RDY and
CE/CS1). This means that the pinctrl subsystem knows that these pins are
in use and cannot be re-assigned as GPIOs for example.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 years ago
Martin Blumenstingl edb0a936f0 lantiq: dts: define the SPI pins in {amazonse,ar9,vr9}.dtsi
Define the SPI pins in the corresponding SoCs.dtsi and assign them to
the SPI controller node. All known boards use CS4 and it's likely that
this is hardcoded in bootrom so this doesn't bother with having
per-board SPI pinmux settings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 years ago
Martin Blumenstingl b3bdfd5df5 lantiq: dts: assign the MDIO pins to the gsw node
Assign the MDIO pins to the switch node instead of using pin hogging
(where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.

This converts amazonse, ar9 and vr9. danube is skipped because the pin
controller doesn't define a pinmux for the MDIO pins (some of the SoC
pads may be hardwired to the MDIO pins instead of being configurable).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 years ago
Mathias Kresin 7685ed59c5 lantiq: dts: add missing size and address cells
Add size and address cells where missing to fix the following devicetree
compiler warning:

  Warning (avoid_default_addr_size): Relying on default #address-cells value
  Warning (avoid_default_addr_size): Relying on default #size-cells value

Signed-off-by: Mathias Kresin <dev@kresin.me>
5 years ago
Mathias Kresin e55827b7a5 lantiq: dts: fix size cells
SPI nodes only need an address and no size. Drop the size everywhere.

Signed-off-by: Mathias Kresin <dev@kresin.me>
5 years ago
Mathias Kresin fcac34d01d lantiq: dts: drop superfluous unit address
The cpu temperature driver has the register offset hardcode and doesn't
need a reg.

The mdio bus node is only used as a well known name and doesn't need a
reg or unit address.

syscon-reboot doesn't have a unit address or a reg either. The unit name
collides with reset-controller@10 anyway.

Signed-off-by: Mathias Kresin <dev@kresin.me>
5 years ago
Mathias Kresin 4053dd3f82 lantiq: dts: add reg if unit address is set
Add the reg property if the node has an unit address. Fixes the
following device tree compiler warning:

  Warning (unit_address_vs_reg): node has a unit name, but no reg property

Signed-off-by: Mathias Kresin <dev@kresin.me>
5 years ago
Mathias Kresin df13384c56 lantiq: dts: move memory node to board dts
The memory node is highly board specific and should be only defined in
the board dts.

Signed-off-by: Mathias Kresin <dev@kresin.me>
5 years ago
Hauke Mehrtens eee1b34ce6 lantiq: copy target to kernel 4.19
This just copies the files from the kernel 4.14 specific folders into
the kernel 4.19 specific folder, no changes are done to the files in
this commit.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
5 years ago