This adds initial support for kernel 4.14 based on the patches for
kernel 4.9.
In the configuration I deactivated some of the new possible security
features like:
CONFIG_REFCOUNT_FULL
CONFIG_SLAB_FREELIST_HARDENED
CONFIG_SOFTLOCKUP_DETECTOR
CONFIG_WARN_ALL_UNSEEDED_RANDOM
And these overlay FS options are also deactivated:
CONFIG_OVERLAY_FS_INDEX
CONFIG_OVERLAY_FS_REDIRECT_DIR
I activated this:
CONFIG_FORTIFY_SOURCE
CONFIG_POSIX_TIMERS
CONFIG_SLAB_MERGE_DEFAULT
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED
I am not sure if I did the porting correct for the following patches:
target/linux/generic/backport-4.14/020-backport_netfilter_rtcache.patch
target/linux/generic/hack-4.14/220-gc_sections.patch
target/linux/generic/hack-4.14/321-powerpc_crtsavres_prereq.patch
target/linux/generic/pending-4.14/305-mips_module_reloc.patch
target/linux/generic/pending-4.14/611-netfilter_match_bypass_default_table.patch
target/linux/generic/pending-4.14/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This patch provides a generic switch_dev_ops 'get_port_stats()' callback by
taping into the relevant port MIB counters.
This callback is used by swconfig_leds led trigger to blink LEDs with port
network traffic.
Signed-off-by: Thibaut VARENE <hacks@slashdirt.org>
Some devices (e.g. Tenda AC9 based on BCM47189B0) have BCM53125 with
port 5 connected to the second Ethernet interface on the SoC. In such
case there is no PHY and we need to force link manually.
This assumes port 5 can be marked as enabled for such devices. It's not
implemented yet unfortunately.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Our code was assuming CPU port uses the highest number. My BCM53573
device has eth0 connected to port 8 and eth1 connected to port 5. While
working on support for it I tried to:
1) Enable all ports (including port 8)
2) Set CPU port to 5
I noticed port 8 is not accessible anymore. It was just a development
process but it seems like something worth fixing anyway.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jonas.gorski@gmail.com>
When dealing with Broadcom hardware we can simply use swconfig's generic
helper, we just need to do some validation of requested state.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48623
Thanks to this change swconfig can access port PHYs e.g. when setting
port link state with a generic helper.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48622
On two tested devices: Netgear R6250 (BCM53011 rev 2) and Luxul XWC-1000
(BCM53011 rev 3) it was possible to use port 7 and eth1 (instead of port
5 and eth0). It seems BCM53011 just like BCM53012 has 8 ports and
usually 3 of them are connected to the SoC.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 46104
On device reset the sizes for the vlan and port tables were wrongly
calculated based on the pointer size instead of the struct size. This
causes buffer overruns on 64 bit targets, resulting in panics.
Fix this by dereferencing the pointers.
Reported-by: Fedor Konstantinov <blmink@mink.su>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45938
This chipset has at least 8 usable ports, e.g. Netgear R8000 has ports
5, 7 and 8 connected to Ethernet interfaces:
vlan1ports=0 1 2 3 5 7 8*
vlan2ports=4 8u
Port 6 seems to be always disabled.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45676
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45402
* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45356
It will now actually enable the mib counters instead of enabling rx/tx for
the first switch port.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44788
The BCM5365 needs a shift of 7 bits and not 6 bits like the BCM5325 for
the untagged ports.
Thank you Russell for reporting this and testing the patch.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 38793
The revision is stored in a different register than it is in other
Broadcom switches.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37995
These switches are integrated in some recent BCM53XX and BCM47XX SoCs
like the BCM53572.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37994
b53_no_ops has no elements and b53_port_ops has one element, this makes
the code access some random memory when trying to access the mib
counter functions.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37895
This is needed for some switches used on bcm47xx SoCs like the one on the Asus RT-N66U.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37645
This makes it possible to use swconfig to controll the switch.
This was tested with devices using b43 and bgmac.
This was not tested on devices using tg3.
This does not support the adm switch used in some very old devices.
SVN-Revision: 37304
Setting this bit stops BCM53125 (bgmac actually) from receiving any
packets. This bit is cleared conditionally in b53_switch_reset and it
seems the same is done in bcmrobo.c which never sets that bit again.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 35723
Add swconfig switch driver for Broadcom BCM53XX switch chips. Supports
switches connected through MDIO, SPI or memory mapped registers, and
supports BCM5325, BCM539x, BCM531x5 and the BCM63XX internal switch
chips.
Tested are BCM5325 trough MDIO, BCM53115 through SPI, and BCM6328.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 35305
Rafał Miłecki
Hauke Mehrtens
Thibaut VARENE
Jonas Gorski
Rafał Miłecki
Jonas Gorski