If the cpu port is connected through SGMII we need to enable SerDes for
it to work.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Acked-by: Felix Fietkau <nbd@nbd.name>
The clearfog u-boot does not initialize the switch at all, so we need to
power up the phys ourselves.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Acked-by: Felix Fietkau <nbd@nbd.name>
The previous "link" and "status" functions were non-standard,
and thus less useful for parsing.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 46864
This also clears any bootloader-set FDB defaults. This had
caused issues creating port-based VLANs when mappings
overlapped previous VLANs. Packets destined to a port
not in the default port group flooded all ports.
Tested on a 88E6171 (Linksys EA4500) and 88E6172 ('1900AC)
Signed-off-by: Claudio Leite <leitec@staticky.com>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
SVN-Revision: 46699
Since the driver doesn't know anything about (M)STP
we just hard-set the ports to be enabled if they are
part of the VLAN.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43938
- eliminate MV_CPUPORT; not necessary since we define
the CPU port(s) via Device Tree
- add STU and expand VTU operations
- update register names to match those of 88E61xx rather than
mvswitch's 88E6060
- use more consistent formatting
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43937
Deng Qingfang
Imre Kaloz
Jonas Gorski
Felix Fietkau
Felix Fietkau
Luka Perkov