Commit Graph

2 Commits (52a0bd33341e11ffbd5b087b4ceb52ca754de8ba)

Author SHA1 Message Date
Pavel Kubelun 2ee98e8f6e ipq40xx: directly define voltage per opp
This should align opp table with what it was before converting to OPP v2.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
5 years ago
Christian Lamparter 18e942b6c4 ipq40xx: fix pcie msi IRQ trigger level
From: Niklas Cassel <niklas.cassel@linaro.org>
|The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
|triggered interrupt.
|
|The msi_ctrl_int will be high for as long as any MSI status bit is set,
|thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
|IRQ handler to keep getting called, as long as any MSI status bit is set.
|[...]
|Not having the correct IRQ type defined will cause us to lose interrupts,
|which in turn causes timeouts in the PCIe endpoint drivers.
|
|Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
|Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
5 years ago