Commit "generic: ar8216: add mib_poll_interval switch attribute" sets
mib-poll-interval as disabled by default (was set to 2s), so it makes
switch LEDs trigger disfunctional on devices which don't have
mib-poll-interval set.
So this patch sets mib-poll-interval to 500ms on devices which have
ar83xx switch connected to mdio0 bus, as the same value was set for
built in switches in 443fc9ac35 ("ath79: use ar8216 for builtin
switch").
Some measurements performed on TP-Link Archer C7-v5:
mib-type=0, mib-poll-interval=500ms (10s pidstat)
Average: %usr %system %guest %wait %CPU CPU Command
Average: 0.00 1.93 0.00 0.00 1.93 - kworker/0:2
iperf3 (30s): 334 Mbits/sec
mib-type=0, mib-poll-interval=2s (10s pidstat)
Average: %usr %system %guest %wait %CPU CPU Command
Average: 0.00 1.14 0.00 0.00 1.14 - kworker/0:2
iperf3 (30s): 334 Mbits/sec
So it seems like we get 4x faster LED refresh rate for additional 0.8%
CPU load.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Simply dumped content of this regs in ar71xx and wrote them to DTS, as a
result port 6 on the switch will appear disconnected as on Archer C7v4.
[AS: testing and PORT6_STATUS fix]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This devices have LEDs connected to the SoC's GPIOs, so it makes no
sense to fiddle with ar8327 LED regs.
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The GPIO for the reset button for the Archer C7v5 changed from
ar71xx to ath79. An investigation based on tests revealed
that the A7v5 responds on "11", while the C7v5 responds on
"5" as set for ar71xx.
Thus, we just define this in the DTS files instead of in the
common DTSI.
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Definition is split here without obvious reason. Just merge it
(and align order to that from C7 v4).
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This patch adds support for TP-Link Archer A7
Specification:
- SOC: QCA9563
- Flash: 16 MiB (SPI)
- RAM: 128 MiB (DDR2)
- Ethernet: 4x 1Gbps LAN + 1x 1Gbps WAN
- Wireless:
- 2.4GHz (bgn) SoC internal
- 5GHz (ac) QCA988x
- USB: 1x USB 2.0 port
- Button: 1x power, 1x reset, 1x wps
- LED: 10x LEDs
- UART: holes in PCB
- Vcc, GND, RX, TX from ethernet port side
- 115200n8
Flash instructions:
Upload openwrt-ath79-generic-tplink_archer-a7-v5-squashfs-factory.bin
via the Webinterface.
Flash instruction using tftp recovery:
1. Connect the computer to one of the LAN ports of the Archer A7
2. Set the computer IP to 192.168.0.66
3. Start a tftp server with the OpenWrt factory image in the tftp
root directory renamed to ArcherC7v5_tp_recovery.bin
2. Connect power cable to Archer A7, press and hold the reset button
and turn the router on
3. Keep the reset button pressed for ~5 seconds
4. Wait ~150 seconds to complete flashing
Changes since first revision:
- Flash instructions using stock image webinterface
- Changed "Version 5" in model string to "v5"
- Split DTS file in qca9563_tplink_archer-x7-v5.dtsi
and qca9563_tplink_archer-a7-v5.dts
- Firmware image is now build with dynamic partitioning
- Default to ath10k-ct
Changes since second revision:
- Changed uboot@0 to uboot@20000 in DTS file
- Fixed ordering issue in board led script
- Specify firmware partition format in DTS file
- Rebased Makefile device definition on common
Device/tplink-safeloader-uimage definition
- Merged switch section in network script
(same configuration as tplink,tl-wdr3600
and tplink,tl-wdr4300)
Signed-off-by: Karl-Felix Glatzer <karl.glatzer@gmx.de>
Petr Štetiar
Adrian Schmutzler
Christian Lamparter
Karl-Felix Glatzer