This patch backports the upstream patch that adds the 4B_OPCODES flag to w25q256 under 4.19 kernel.
This is needed for ipq40xx and ramips.
Signed-off-by: Robert Marko <robimarko@gmail.com>
This target was switched to kernel 4.19 more than 6 months ago in commit
f342ffd300 ("treewide: kernel: bump some targets to 4.19") and now
with kernel 5.4 support being added it gets harder to support kernel
4.14 in addition to kernel 4.19 and 5.4.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Generate a cpximg that is compatible with the cpximg loader in Compex' u-boot.
The cpximg loader can be started either by holding the reset button during power
up or by entering the u-boot prompt and entering 'cpximg'.
Once it's running, a TFTP-server under 192.168.1.1 will accept an image
appropriate for the board revision that is etched on the board (e.g. 6A04).
The image can be pushed using tftp:
tftp -v -m binary 192.168.1.1 -c put openwrt-ipq40xx-generic-compex_wpj428-squashfs-cpximg-6a04.bin
cpximg files can also be used with the sysupgrade utility in stock images.
(add SSH key in luci for root access)
In mkmylofw_32m, the calculation of the "partition size" has been preferred
to just padding the partition as this will result in less block transfers
during flashing (while the additional complexity is bearable).
Signed-off-by: Leon M. George <leon@georgemail.eu>
Co-developed-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This patch adds support for the 8devices Habanero development board.
Specs are:
CPU: QCA IPQ4019
RAM: DDR3L 512MB
Storage: 32MB SPI-NOR and optional Parallel SLC NAND(Some boards ship with it and some without)
WLAN1: 2.4 GHz built into IPQ4019 (802.11n) 2x2
WLAN2: 5 GHz built into IPO4019 (802.11ac Wawe-2) 2x2
Ethernet: 5x Gbit LAN (QCA 8075)
USB: 1x USB 2.0 and 1x USB 3.0 (Both built into IPQ4019)
MicroSD slot (Uses SD controller built into IPQ4019)
SDIO3.0/EMMC slot (Uses the same SD controller)
Mini PCI-E Gen 2.0 slot (Built into IPQ4019)
5x LEDs (4 GPIO controllable)
2x Pushbutton (1 is connected to GPIO, other to SoC reset)
LCD ZIF socket (Uses the LCD controller built into IPQ4019 which has no driver support)
1x UART 115200 rate on J18
2x breakout development headers
12V DC Jack for power
DIP switch for bootstrap configuration
Installation instructions:
Since boards ship with vendors fork of OpenWrt sysupgrade can be used.
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit finally adds support for the built in SD/MMC controller in IPQ4019 SoC.
Controller is supported by the upstream SDHCI-MSM driver with a minor clock setting patch.
Patch is special to the IPQ4019 and cannot be upstreamed.
LDO and SDHCI node are upstreamed, and LDO node is awaiting to be accepted.
Signed-off-by: Robert Marko <robimarko@gmail.com>
This fixes a typo in the device string for MAC address setup in
02_network and corrects the indent in the device's DTS files.
While at it, move the aliases section before the keys section to
have it closer to the top of the file.
Fixes: a736d912e2 ("ipq40xx: add support for EnGenius EAP2200")
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This patch just refreshes the 5.4 patches. It seems as if
070-v4.20-soc-qcom-spm-add-SCM-probe-dependency.patch is
already applied, so drop it. It also does a quick
make kernel_oldconfig to get rid of unneeded symbols.
[Looks like USB and Ethernet need some more work].
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This backports commits from master that fix AES ciphers when using the
qce driver:
- A couple of simple fixes for CTR and XTS modes used with AES:
* 041-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch
* 042-crypto-qce-fix-xts-aes-qce-key-sizes.patch
- A fix for a bug that affected cases when there were more entries in
the input sg list than necessary to actually encrypt, resulting in
failure in gcm, where the authentication tag is present after the
encryption data:
* 043-crypto-qce-save-a-sg-table-slot-for-result-buf.patch
- A fix to update the IV buffer passed to the driver from the kernel:
* 044-crypto-qce-update-the-skcipher-IV.patch
- A patch that reduces memory footprint and driver initialization by
only initializing the fallback mechanism where it is actually used:
* 046-crypto-qce-initialize-fallback-only-for-AES.patch
- Three patches that make gcm and xts modes work with the qce driver,
and improve performance with small blocks:
* 047-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch
* 048-crypto-qce-use-AES-fallback-for-small-requests.patch
* 049-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch
- A patch that allows the hashes/ciphers to be built individually.
* 051-crypto-qce-allow-building-only-hashes-ciphers.patch
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[renumbered patches, added patches from dropped commit, refreshed, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This backports a commit updating the API of the QCE crypto engine to
what is used in current kerenl, easing future upstream backports.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[renumber patches, refreshed, added 5.4 patches]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
SOC: IPQ4019 / QCA Dakota
CPU: Quad-Core ARMv7 Processor rev 5 (v7l) Cortex-A7
DRAM: 256 MiB
FLASH: NOR 4 MiB + NAND 128 MiB
ETH: Qualcomm Atheros QCA8072
WLAN1: Qualcomm Atheros QCA4019 2.4GHz 802.11bgn 2:2x2
WLAN2: Qualcomm Atheros QCA4019 5GHz 802.11a/n/ac 2:2x2
WLAN2: Qualcomm Atheros QCA9888 5GHz 802.11a/n/ac 2:2x2
INPUT: WPS Button
LEDS: Power, LAN1, LAN2, WLAN 2.4GHz, WLAN 5GHz-1, WLAN 5GHz-2, OPMODE
1. Load Ramdisk via U-Boot
To set up the flash memory environment, do the following:
a. As a preliminary step, ensure that the board console port is connected to the PC using these RS232 parameters:
* 115200bps
* 8N1
b. Confirm that the PC is connected to the board using one of the Ethernet ports.
c. Set a static ip 192.168.99.8 for Ethernet that connects to board.
d. The PC must have a TFTP server launched and listening on the interface to which the board is connected.
e. At this stage power up the board and, after a few seconds, press 4 and then any key during the countdown.
U-BOOT> set serverip 192.168.99.9 && tftpboot 0x84000000 192.168.99.8:openwrt.itb && bootm
Signed-off-by: Steven Lin <steven.lin@senao.com>
[copied 4.19 dts to 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This patch fixes the occurences of the following warning
message from the dtc:
Warning (reg_format): /soc/spi@78b5000/flash0@0/partitions/partition@0:reg:
property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
SOC: IPQ4018 / QCA Dakota
CPU: Quad-Core ARMv7 Processor rev 5 (v7l) Cortex-A7
DRAM: 256 MiB
NOR: 32 MiB
ETH: Qualcomm Atheros QCA8072 (1 port)
WLAN1: Qualcomm Atheros QCA4018 2.4GHz 802.11bgn 2:2x2
WLAN2: Qualcomm Atheros QCA4018 5GHz 802.11a/n/ac 2:2x2
INPUT: RESET Button
LEDS: White, Blue, Red, Orange
Flash instruction:
From EnGenius firmware to OpenWrt firmware:
In Firmware Upgrade page, upgrade your openwrt-ipq40xx-generic-engenius_emd1-squashfs-factory.bin directly.
From OpenWrt firmware to EnGenius firmware:
1. Setup a TFTP server on your computer and configure static IP to 192.168.99.8
Put the EnGenius firmware in the TFTP server directory on your computer.
2. Power up EMD1. Press 4 and then press any key to enter u-boot.
3. Download EnGenius firmware
(IPQ40xx) # tftpboot 0x84000000 openwrt-ipq40xx-emd1-nor-fw-s.img
4. Flash the firmware
(IPQ40xx) # imgaddr=0x84000000 && source 0x84000000:script
5. Reboot
(IPQ40xx) # reset
Signed-off-by: Yen-Ting-Shen <frank.shen@senao.com>
[removed BOARD_NAME]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Specifications
==============
- SOC: IPQ4018
- RAM: DDR3 256MB
- Flash: SPI NOR 16MB
- WiFi:
- 2.4GHz: IPQ4018, 2x2, front end SKY85303-11
- 5GHz: IPQ4018, 2x2, front end SKY85717-21
- Ethernet: 1x 10/100/1000Mbps, POE 802.3af
- PHY: QCA8072
- UART: GND, blocked, 3.3V, RX, TX / 115200 8N1
- LED: 1x red / green
- Button: 1x reset / factory default
- U-Boot bootloader with tftp and "emergency web server" accessible
using serial port.
Installation
============
Flash factory image from D-Link web UI. Constraints in the D-Link web UI
makes the factory image unnecessarily large. Flash again using
sysupgrade from inside OpenWrt to reclaim some flash space.
Return to stock D-Link firmware
===============================
Partition layout is preserved, and it is possible to return to the stock
firmware simply by downloading it from D-Link and writing it to the
firmware partition.
# mtd -r write dap2610-firmware.bin firmware
Quirks
======
To be flashable from the D-Link http server, the firmware must be larger
then 6MB, and the size in the firmware header must match the actual file
size. Also, the boot loader verifies the checksum of the firmware before
each boot, thus the jffs2 must be after the checksum covered part. This
is solved in the factory image by having the rootfs at the very end of
the image (without pad-rootfs).
The sysupgrade image which does not have to be flashable from the D-Link
web UI may be smaller, and the checksum in the firmware header only
covers the kernel part of the image.
Signed-off-by: Fredrik Olofsson <fredrik.olofsson@anyfinetworks.com>
[added WRGG Variables to DEVICE_VARS, squashed spi pinconf/mux,
added emd1's gmac0 config,fix dtc warnings]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
The Aruba AP-303H is the hospitality version of the Aruba AP-303 with a
POE-passthrough enabled ethernet switch instead of a sigle PHY.
Hardware
--------
SoC: Qualcomm IPQ4029
RAM: 512M DDR3
FLASH: - 128MB SPI-NAND (Macronix)
- 4MB SPI-NOR (Macronix MX25R3235F)
TPM: Atmel AT97SC3203
BLE: Texas Instruments CC2540T
attached to ttyMSM1
ETH: Qualcomm QCA8075
LED: WiFi (amber / green)
System (red / green /amber)
PSE (green)
BTN: Reset
USB: USB 2.0
To connect to the serial console, you can solder to the labled pads next
to the USB port or use your Aruba supplied UARt adapter.
Do NOT plug a standard USB cable into the Console labled USB-port!
Aruba/HPE simply put UART on the micro-USB pins. You can solder yourself
an adapter cable:
VCC - NC
D+ - TX
D- - RX
GND - GND
The console setting in bootloader and OS is 9600 8N1. Voltage level is
3.3V.
To enable a full list of commands in the U-Boot "help" command, execute
the literal "diag" command.
Installation
------------
1. Get the OpenWrt initramfs image. Rename it to ipq40xx.ari and put it
into the TFTP server root directory. Configure the TFTP server to
be reachable at 192.168.1.75/24. Connect the machine running the TFTP
server to the E0 (!) ethernet port of the access point, as it only
tries to pull from the WAN port.
2. Connect to the serial console. Interrupt autobooting by pressing
Enter when prompted.
3. Configure the bootargs and bootcmd for OpenWrt.
$ setenv bootargs_openwrt "setenv bootargs console=ttyMSM0,9600n8"
$ setenv nandboot_openwrt "run bootargs_openwrt; ubi part aos1;
ubi read 0x85000000 kernel; set fdt_high 0x87000000;
bootm 0x85000000"
$ setenv ramboot_openwrt "run bootargs_openwrt;
setenv ipaddr 192.168.1.105; setenv serverip 192.168.1.75;
netget; set fdt_high 0x87000000; bootm"
$ setenv bootcmd "run nandboot_openwrt"
$ saveenv
4. Load OpenWrt into RAM:
$ run ramboot_openwrt
5. After OpenWrt booted, transfer the OpenWrt sysupgrade image to the
/tmp folder on the device. You will need to plug into E1-E3 ports of
the access point to reach OpenWrt, as E0 is the WAN port of the
device.
6. Flash OpenWrt:
$ ubidetach -p /dev/mtd16
$ ubiformat /dev/mtd16
$ sysupgrade -n /tmp/openwrt-sysupgrade.bin
To go back to the stock firmware, simply reset the bootcmd in the
bootloader to the original value:
$ setenv bootcmd "boot"
$ saveenv
Signed-off-by: David Bauer <mail@david-bauer.net>
Hardware:
SOC: Qualcomm IPQ4018
RAM: 128 MB Nanya NT5CC64M16GP-DI
FLASH: 16 MB Macronix MX25L12805D
ETH: Qualcomm QCA8075 (4 Gigabit ports, 3xLAN, 1xWAN)
WLAN: Qualcomm IPQ4018 (2.4 & 5 Ghz)
BUTTON: Shared WPS/Reset button
LED: RGB Status/Power LED
SERIAL: Header J8 (UART, Left side of board). Numbered from
top to bottom:
(1) GND, (2) TX, (3) RX, (4) VCC (White triangle
next to it).
3.3v, 115200, 8N1
Tested/Working:
* Ethernet
* WiFi (2.4 and 5GHz)
* Status LED
* Reset Button (See note below)
Implementation notes:
* The shared WPS/Reset button is implemented as a Reset button
* I could not find a original firmware image to reverse engineer, meaning
currently it's not possible to flash OpenWrt through the Web GUI.
Installation (Through Serial console & TFTP):
1. Set your PC to fixed IP 192.168.1.12, Netmask 255.255.255.0, and connect to
one of the LAN ports
2. Rename the initramfs image to 'C0A8010B.img' and enable a TFTP server on
your pc, to serve the image
2. Connect to the router through serial (See connection properties above)
3. Hit a key during startup, to pause startup
4. type `setenv serverip 192.168.1.12`, to set the tftp server address
5. type `tftpboot`, to load the image from the laptop through tftp
6. type `bootm` to run the loaded image from memory
6. (If you want to return to stock firmware later, create an full MTD backup,
e.g. using instructions here https://openwrt.org/docs/guide-user/installation/generic.backup#create_full_mtd_backup)
7. Transfer the 'sysupgrade' OpenWrt firmware image from PC to router, e.g.:
`scp xxx-squashfs-sysupgrade.bin root@192.168.1.1:/tmp/upgrade.bin`
8. Run sysupgrade to permanently install OpenWrt to flash: `sysupgrade -n /tmp/upgrade.bin`
Revert to stock:
To revert to stock, you need the MTD backup from step 6 above:
1. Unpack the MTD backup archive
2. Transfer the 'firmware' partition image to the router (e.g. mtd8_firmware.backup)
3. On the router, do `mtd write mtd8_firmware.backup firmware`
Signed-off-by: Tom Brouwer <tombrouwer@outlook.com>
[removed BOARD_NAME, OpenWRT->OpenWrt, changed LED device name to board name]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This patch partially reverts
"ipq40xx: remove unnecessary usb nodes in DTS for ASUS RT-AC58U"
as the change removed the usb2 port-trigger, so the LED would no
longer light-up when a USB 2.0 was inserted into the USB port.
Fixes: d0efb1ba95 ("ipq40xx: remove unnecessary usb nodes in DTS for ASUS RT-AC58U")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This patch uses the SOC variable to calculate DTS names automatically
based on the SOC and the device definition node name.
This reduces redundancy and (by having to choose DTS name
appropriately) will unify the naming of a device in different places
(image/Makefile, DTS name, compatible, image name). This is supposed
to make life easier for developers and reviewers.
Since the kernel uses a "soc-device.dts" scheme for this target, we
use this for the derivation of DEVICE_DTS, too, and rename the files
not having followed it so far.
Note that for some devices the kernel itself is inconsistent, leaving
us with a manual overwrite for ap.dk01.1-c1 and ap.dk04.1-c1.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Deactivate CONFIG_SFP for kernel 4.19 in the generic configuration.
The CONFIG_SFP configuration option was not set to anything in the
ath79 build for me, set it to deactivated by default.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This patch does the following:
- move WiFi LED setup to DTS
- fix LAN/WAN MAC addresses and add label MAC address
- wan5G -> wlan5G, power -> led_power
- increase flash SPI frequency to 30MHz
MAC addresses are stored in Factory partition at:
0x1006: WiFi 2.4GHz, WAN (label_mac)
0x5006: WiFi 5GHz, LAN (label_mac +4)
By improving flash speed,
`time dd if=/dev/mtdblock8 of=/dev/null bs=2k`
is reduced from 7m 10.26s to 5m 9.52s.
Using higher frequencies did not improve speed further.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Hardware
--------
SoC: Qualcomm IPQ4029
RAM: 512M DDR3
FLASH: - 128MB NAND (Macronix MX30LF1G18AC)
- 4MB SPI-NOR (Macronix MX25R3235F)
TPM: Atmel AT97SC3203
BLE: Texas Instruments CC2540T
attached to ttyMSM0
ETH: Atheros AR8035
LED: WiFi (amber / green)
System (red / green)
BTN: Reset
To connect to the serial console, you can solder to the labled pads next
to the USB port or use your Aruba supplied UARt adapter.
Do NOT plug a standard USB cable into the Console labled USB-port!
Aruba/HPE simply put UART on the micro-USB pins. You can solder yourself
an adapter cable:
VCC - NC
D+ - TX
D- - RX
GND - GND
The console setting in bootloader and OS is 9600 8N1. Voltage level is
3.3V.
To enable a full list of commands in the U-Boot "help" command, execute
the literal "diag" command.
Installation
------------
1. Get the OpenWrt initramfs image. Rename it to ipq40xx.ari and put it
into the TFTP server root directory. Configure the TFTP server to
be reachable at 192.168.1.75/24. Connect the machine running the TFTP
server to the ethernet port of the access point.
2. Connect to the serial console. Interrupt autobooting by pressing
Enter when prompted.
3. Configure the bootargs and bootcmd for OpenWrt.
$ setenv bootargs_openwrt "setenv bootargs console=ttyMSM1,9600n8"
$ setenv nandboot_openwrt "run bootargs_openwrt; ubi part aos1;
ubi read 0x85000000 kernel; bootm 0x85000000"
$ setenv ramboot_openwrt "run bootargs_openwrt;
setenv ipaddr 192.168.1.105; setenv serverip 192.168.1.75;
netget; set fdt_high 0x87000000; bootm"
$ setenv bootcmd "run nandboot_openwrt"
$ saveenv
4. Load OpenWrt into RAM:
$ run ramboot_openwrt
5. After OpenWrt booted, transfer the OpenWrt sysupgrade image to the
/tmp folder on the device.
6. Flash OpenWrt:
$ ubidetach -p /dev/mtd1
$ ubiformat /dev/mtd1
$ sysupgrade -n /tmp/openwrt-sysupgrade.bin
To go back to the stock firmware, simply reset the bootcmd in the
bootloader to the original value:
$ setenv bootcmd "boot"
$ saveenv
Signed-off-by: David Bauer <mail@david-bauer.net>
MeshPoint.One is Wi-Fi hotspot and smart IoT gateway (based upon
Jalapeno module from 8Devices).
MeshPoint.One (https://meshpointone.com) is a unique Wi-Fi hotspot and
smart city gateway that can be installed and powered from street
lighting (even solar power in the future). MeshPoint provides up to 27
hours of interrupted Wi-Fi and IoT services from internal battery even
when external power is not available. MeshPoint.One can be used for
disaster relief efforts in order to provide instant Wi-Fi coverage that
can be easily expanded by just adding more devices that create wide area
mesh network. MeshPoint.One devices have standard Luci UI for
management.
Features:
- 1x 1Gpbs WAN
- 1x 1Gbps LAN
- POE input (eth0)
- POE output (eth1)
- Sensor for temperature, humidity and pressure (Bosch BME280)
- current, voltage and power measurement via TI INA230
- Hardware real time clock
- optional power via Li-Ion battery
- micro USB port with USB to serial chip for easy OpenWrt terminal
access
- I2C header for connecting additional sensors
Installation:
-------------
Simply flash the sysupgrade image from stock firmware.
Or use the built in Web recovery into bootloader:
Hold Reset button for 5 to 20 seconds or use UART and httpd command.
Web UI will appear on 192.168.2.100 by default.
For web recovery use the factory.ubi image.
Signed-off-by: Damir Samardzic <damir.samardzic@sartura.hr>
Signed-off-by: Damir Franusic <damir.franusic@sartura.hr>
Signed-off-by: Valent Turkovic <valent@meshpoint.me>
Signed-off-by: Robert Marko <robert@meshpoint.me>
[commit description long line wrap, usb->USB]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Lets move common code for Jalapeno into DTSI, this way Jalapeno based
boards don't introduce duplicate code.
While at it, lets also fix some style issues and update to current DTS
style.
Signed-off-by: Robert Marko <robert@meshpoint.me>
[commit description long line wrap]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Use reset-gpio instead of the custom phy-reset-gpio property to do phy
reset on the U4019. phy-reset-gpio was incorrectly introduced when we
added support for the U4019, and will be deprecated.
Signed-off-by: Kristian Evensen <kristian.evensen@gmail.com>
The old GPIO based phy reset (phy-reset-gpio) will be removed form
the ipq40xx mdio driver in the future.
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
Commit 6f6c00cfc9 ("ipq40xx: Add support for Unielec U4019") has
introduced support for `phy-reset-gpio` DT property, which isn't needed
as the MDIO already supports `reset-gpios`[1] which could be used instead.
1. https://elixir.bootlin.com/linux/v4.19.81/source/Documentation/devicetree/bindings/net/mdio.txt
Ref: PR#2511
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
[commit title and description facelift]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This cosmetical patch converts IMAGE_SIZE, KERNEL_SIZE and
BLOCKSIZE definitions to kilobytes, as this is consistent and
easier to read/type.
An exception was made for asus_rt-ac58u, where the IMAGE_SIZE of
20439364 cannot be divided by 1024 (and also does not seem to
match anything in DTS).
Build-tested for all devices.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This device contains 2 flash devices. One NOR (32M) and one NAND (128M).
U-boot and caldata are on the NOR, the firmware on the NAND.
SoC: IPQ4019
CPU: 4x 710MHz ARMv7
RAM: 256MB
FLASH: NOR:32MB NAND:128MB
ETH: 2x GMAC Gigabit
POE: 802.3 af/at POE, IEEE802.3af/IEEE802.3at(48-56V)
WIFI: 1x 2.4Ghz Atheros qca4019 2x2 MU-MIMO
1x 5.0Ghz Atheros qca4019 2x2 MU-MIMO
USB: 1x 3.0
PCI: 1x Mini PCIe
SIM: 1x Slot
SD: 1x MicroSD slot
BTN: Reset
LED: - Power
- Ethernet
UART: 1x Serial Port 4 Pin Connector (UART)
1x Serial Port 6 Pin Connector (High Speed UART)
POWER: 12V 2A
Installation
------------
Initial flashing can only be done via u-boot using the following commands:
tftpboot openwrt-ipq40xx-generic-compex_wpj419-squashfs-nand-factory.ubi
nand erase.chip; nand write ${fileaddr} 0x0 ${filesize}
res
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
This is based on the EX6150v2, which should be identical to
the EX6100v2:
The device bears two MAC addresses ("MAC 1" and "MAC 2") that
correspond to phy0 and phy1.
The ethernet MAC address (gmac0) is the same as phy0.
As this one is accessible via local-mac-address in gmac0, the
latter is used for label-mac-device.
(Although this is a one-port, gmac1 also has a local-mac-address
assigned. This has the same vendor part as the other addresses,
but completely different data for the device part.)
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
If flash size is used as part of a device's title, it should be
specified as DEVICE_VARIANT like for the other devices so far.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
generic: Add/rename patches for upstream consistency
ipq40xx: generic-level patch replaces same-source patches-4.19/
082-v4.20-mtd-spinand-winbond-Add-support-for-W25N01GV.patch
The SPI-NAND framework from Linux uses common driver code that is then
"tuned" by a tiny struct of chip-specific data that describes
available commands, timing, and layout (data and OOB data). Several
manufacturers and chips have been added since 4.19, several of which
are used in devices already supported by OpenWrt (typically with no or
"legacy" access to their NAND memory). This commit catches up the
supported-chip definitions through Linux 5.2-rc6 and linux/next.
The driver is only compiled for platforms with CONFIG_MTD_SPI_NAND=y.
This presently includes ipq40xx and pistachio, with the addition of
ath79-nand in these commits (and not ath79-generic or ath79-tiny).
Upstream patches refreshed against 4.19.75
Build-tested-on: ipq40xx
Run-tested-on: ath79-nand
Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
Robert Marko
Hauke Mehrtens
Sungbo Eo
Leon M. George
Yousong Zhou
Koen Vandeputte
Adrian Schmutzler
David Bauer
Christian Lamparter
Eneas U de Queiroz
Steven Lin
John Crispin
Yen-Ting-Shen
Fredrik Olofsson
Tom Brouwer
Paul Fertser
Robert Marko
Kristian Evensen
Daniel Danzberger
DENG Qingfang
Jeff Kletsky