openwrt

Commit Graph

Author	SHA1	Message	Date
Sven Eckelmann	b1d57dadb2	ar71xx: disable 40Mhz refclk for QCA953x The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms" datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a 40 Mhz reference clock. The register description for "Bootstrap Options" (page 31) defines following states for the bit 4 (REF_CLK): * 0 - CLK25 (default) * 1 - (reserved) Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25 Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and then break the bootup of the system due to this incorrect interpretation. Signed-off-by: Sven Eckelmann <sven@narfation.org> [refreshed patches] Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>	6 years ago
Matthias Schiffer	d04056e5ea	ar71xx: disable devicetree support While we'd like to convert ar71xx to DT-based configuration eventually, we aren't quite there yet, and shipping half-baked DT support that is not used at all wastes precious space. Saves ~120KB before LZMA, ~33KB after LZMA. Run-tested on TP-Link CPE510 and TL-WR841 v7. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>	7 years ago
Hauke Mehrtens	7bbf4117c6	ar71xx: Add kernel 4.9 support This add support for kernel 4.9 to the ar71xx target. It was compile tested with the generic, NAND and mikrotik subtarget. Multiple members of the community tested it on their boards and did not report any major problem so far. Especially the NAND part received some changes to adapt to the new kernel APIs. The serial driver hack used for the Arduino Yun was not ported because the kernel changed there a lot. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>	7 years ago

Author

SHA1

Message

Date

Sven Eckelmann

b1d57dadb2

ar71xx: disable 40Mhz refclk for QCA953x

The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):

* 0 - CLK25 (default)
* 1 - (reserved)

Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>

Matthias Schiffer

d04056e5ea

ar71xx: disable devicetree support

While we'd like to convert ar71xx to DT-based configuration
eventually, we aren't quite there yet, and shipping half-baked DT support
that is not used at all wastes precious space.

Saves ~120KB before LZMA, ~33KB after LZMA.

Run-tested on TP-Link CPE510 and TL-WR841 v7.

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

Hauke Mehrtens

7bbf4117c6

ar71xx: Add kernel 4.9 support

This add support for kernel 4.9 to the ar71xx target.
It was compile tested with the generic, NAND and mikrotik subtarget.
Multiple members of the community tested it on their boards and did not
report any major problem so far.

Especially the NAND part received some changes to adapt to the new
kernel APIs. The serial driver hack used for the Arduino Yun was not
ported because the kernel changed there a lot.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

3 Commits (050da2107a7eb2a571a8a3d0cee21cc6a44b72b8)