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@ -830,7 +830,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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--- a/drivers/pci/dwc/pci-dra7xx.c
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+++ b/drivers/pci/dwc/pci-dra7xx.c
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@@ -338,15 +338,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
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@@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
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return IRQ_HANDLED;
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}
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@ -1125,49 +1125,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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struct pci_epf_header *hdr)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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@@ -74,8 +106,7 @@ static int dw_pcie_ep_inbound_atu(struct
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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- free_win = find_first_zero_bit(&ep->ib_window_map,
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- sizeof(ep->ib_window_map));
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+ free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
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if (free_win >= ep->num_ib_windows) {
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dev_err(pci->dev, "no free inbound window\n");
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return -EINVAL;
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@@ -89,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct
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}
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ep->bar_to_atu[bar] = free_win;
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- set_bit(free_win, &ep->ib_window_map);
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+ set_bit(free_win, ep->ib_window_map);
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return 0;
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}
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@@ -100,8 +131,7 @@ static int dw_pcie_ep_outbound_atu(struc
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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- free_win = find_first_zero_bit(&ep->ob_window_map,
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- sizeof(ep->ob_window_map));
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+ free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
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if (free_win >= ep->num_ob_windows) {
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dev_err(pci->dev, "no free outbound window\n");
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return -EINVAL;
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@@ -110,30 +140,35 @@ static int dw_pcie_ep_outbound_atu(struc
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dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
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phys_addr, pci_addr, size);
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- set_bit(free_win, &ep->ob_window_map);
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+ set_bit(free_win, ep->ob_window_map);
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ep->outbound_addr[free_win] = phys_addr;
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@@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc
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return 0;
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}
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-static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
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+static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
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+ struct pci_epf_bar *epf_bar)
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+ struct pci_epf_bar *epf_bar)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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@ -1178,14 +1142,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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+ __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
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- clear_bit(atu_index, &ep->ib_window_map);
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+ clear_bit(atu_index, ep->ib_window_map);
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|
|
clear_bit(atu_index, ep->ib_window_map);
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}
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-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
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- dma_addr_t bar_phys, size_t size, int flags)
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+static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
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+ struct pci_epf_bar *epf_bar)
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+ struct pci_epf_bar *epf_bar)
|
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|
|
|
{
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|
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int ret;
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|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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|
@ -1196,7 +1159,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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|
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enum dw_pcie_as_type as_type;
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|
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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|
@@ -142,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
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|
@@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
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else
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as_type = DW_PCIE_AS_IO;
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@ -1219,7 +1182,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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|
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dw_pcie_dbi_ro_wr_dis(pci);
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|
return 0;
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|
@@ -169,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
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|
@@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
|
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|
|
return -EINVAL;
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|
|
}
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|
@ -1229,101 +1192,96 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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|
|
{
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|
|
|
|
int ret;
|
|
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|
|
u32 atu_index;
|
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|
|
|
@@ -181,10 +224,11 @@ static void dw_pcie_ep_unmap_addr(struct
|
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|
|
return;
|
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|
|
|
|
dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
|
|
|
|
|
- clear_bit(atu_index, &ep->ob_window_map);
|
|
|
|
|
+ clear_bit(atu_index, ep->ob_window_map);
|
|
|
|
|
@@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct
|
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|
|
|
clear_bit(atu_index, ep->ob_window_map);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
|
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|
|
|
- u64 pci_addr, size_t size)
|
|
|
|
|
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
|
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|
|
|
+ phys_addr_t addr,
|
|
|
|
|
u64 pci_addr, size_t size)
|
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|
|
|
+ phys_addr_t addr,
|
|
|
|
|
+ u64 pci_addr, size_t size)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
@@ -200,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
|
|
|
|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
@@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
|
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|
|
|
return 0;
|
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|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_get_msi(struct pci_epc *epc)
|
|
|
|
|
+static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
|
|
|
|
|
{
|
|
|
|
|
- int val;
|
|
|
|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+{
|
|
|
|
|
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+ u32 val, reg;
|
|
|
|
|
+
|
|
|
|
|
+ if (!ep->msi_cap)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
|
|
|
|
|
- if (!(val & MSI_CAP_MSI_EN_MASK))
|
|
|
|
|
+
|
|
|
|
|
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
|
|
|
|
|
+ val = dw_pcie_readw_dbi(pci, reg);
|
|
|
|
|
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
|
|
|
|
|
+
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
|
|
|
|
|
+ return val;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
|
|
|
|
|
{
|
|
|
|
|
- int val;
|
|
|
|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+{
|
|
|
|
|
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+ u32 val, reg;
|
|
|
|
|
+
|
|
|
|
|
+ if (!ep->msi_cap)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
|
|
|
|
|
- val &= ~MSI_CAP_MMC_MASK;
|
|
|
|
|
- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
|
|
|
|
|
+
|
|
|
|
|
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
|
|
|
|
|
+ val = dw_pcie_readw_dbi(pci, reg);
|
|
|
|
|
+ val &= ~PCI_MSI_FLAGS_QMASK;
|
|
|
|
|
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
|
|
|
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
|
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
|
|
|
|
|
+ dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
|
+ dw_pcie_writew_dbi(pci, reg, val);
|
|
|
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
|
|
|
|
|
- enum pci_epc_irq_type type, u8 interrupt_num)
|
|
|
|
|
+ dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
|
+
|
|
|
|
|
+ return 0;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
|
|
|
|
|
+{
|
|
|
|
|
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
{
|
|
|
|
|
- int val;
|
|
|
|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+ u32 val, reg;
|
|
|
|
|
+
|
|
|
|
|
+ if (!ep->msix_cap)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
|
|
|
|
|
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
|
|
|
|
|
- if (!(val & MSI_CAP_MSI_EN_MASK))
|
|
|
|
|
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
|
|
|
|
|
+ val = dw_pcie_readw_dbi(pci, reg);
|
|
|
|
|
+ if (!(val & PCI_MSIX_FLAGS_ENABLE))
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
|
|
|
|
|
+ val &= PCI_MSIX_FLAGS_QSIZE;
|
|
|
|
|
+
|
|
|
|
|
+ return val;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
|
|
|
|
|
+static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
|
|
|
|
|
+{
|
|
|
|
|
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
{
|
|
|
|
|
- int val;
|
|
|
|
|
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
+ u32 val, reg;
|
|
|
|
|
+
|
|
|
|
|
|
|
|
|
|
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
|
|
|
|
|
- val &= ~MSI_CAP_MMC_MASK;
|
|
|
|
|
- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
|
|
|
|
|
+ if (!ep->msix_cap)
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
+
|
|
|
|
|
@ -1331,13 +1289,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
|
|
|
+ val = dw_pcie_readw_dbi(pci, reg);
|
|
|
|
|
+ val &= ~PCI_MSIX_FLAGS_QSIZE;
|
|
|
|
|
+ val |= interrupts;
|
|
|
|
|
+ dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
|
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
|
|
|
|
|
+ dw_pcie_writew_dbi(pci, reg, val);
|
|
|
|
|
+ dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
|
+
|
|
|
|
|
+ return 0;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
|
|
|
|
|
- enum pci_epc_irq_type type, u8 interrupt_num)
|
|
|
|
|
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
|
|
|
|
|
+ enum pci_epc_irq_type type, u16 interrupt_num)
|
|
|
|
|
{
|
|
|
|
|
@ -1351,7 +1312,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dw_pcie_ep_stop(struct pci_epc *epc)
|
|
|
|
|
@@ -271,15 +363,130 @@ static const struct pci_epc_ops epc_ops
|
|
|
|
|
@@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops
|
|
|
|
|
.unmap_addr = dw_pcie_ep_unmap_addr,
|
|
|
|
|
.set_msi = dw_pcie_ep_set_msi,
|
|
|
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.get_msi = dw_pcie_ep_get_msi,
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@ -1482,7 +1443,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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pci_epc_mem_exit(epc);
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}
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@@ -293,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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@@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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struct device_node *np = dev->of_node;
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if (!pci->dbi_base || !pci->dbi_base2) {
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@ -1491,40 +1452,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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return -EINVAL;
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}
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@@ -302,12 +509,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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dev_err(dev, "unable to read *num-ib-windows* property\n");
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return ret;
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}
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+ if (ep->num_ib_windows > MAX_IATU_IN) {
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+ dev_err(dev, "invalid *num-ib-windows*\n");
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+ return -EINVAL;
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+ }
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ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ob-windows* property\n");
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return ret;
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}
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+ if (ep->num_ob_windows > MAX_IATU_OUT) {
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+ dev_err(dev, "invalid *num-ob-windows*\n");
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+ return -EINVAL;
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+ }
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+
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+ ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
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+ BITS_TO_LONGS(ep->num_ib_windows),
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+ GFP_KERNEL);
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+ if (!ep->ib_window_map)
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+ return -ENOMEM;
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+
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+ ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
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+ BITS_TO_LONGS(ep->num_ob_windows),
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+ GFP_KERNEL);
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+ if (!ep->ob_window_map)
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+ return -ENOMEM;
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addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
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GFP_KERNEL);
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@@ -315,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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@@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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return -ENOMEM;
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ep->outbound_addr = addr;
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@ -1546,7 +1474,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
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if (ret < 0)
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epc->max_functions = 1;
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@@ -335,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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@@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
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return ret;
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}
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@ -1873,9 +1801,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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|
|
/*
|
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* Maximum number of MSI IRQs can be 256 per controller. But keep
|
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* it 32 as of now. Probably we will never need more than 32. If needed,
|
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@@ -114,6 +102,10 @@
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|
#define MAX_MSI_IRQS 32
|
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|
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
|
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@@ -118,6 +106,10 @@
|
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|
|
#define MAX_IATU_IN 256
|
|
|
|
|
#define MAX_IATU_OUT 256
|
|
|
|
|
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|
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|
|
+/* Maximum number of inbound/outbound iATUs */
|
|
|
|
|
+#define MAX_IATU_IN 256
|
|
|
|
|
@ -1884,7 +1812,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
|
|
|
struct pcie_port;
|
|
|
|
|
struct dw_pcie;
|
|
|
|
|
struct dw_pcie_ep;
|
|
|
|
|
@@ -181,8 +173,8 @@ enum dw_pcie_as_type {
|
|
|
|
|
@@ -185,8 +177,8 @@ enum dw_pcie_as_type {
|
|
|
|
|
|
|
|
|
|
struct dw_pcie_ep_ops {
|
|
|
|
|
void (*ep_init)(struct dw_pcie_ep *ep);
|
|
|
|
|
@ -1895,24 +1823,18 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct dw_pcie_ep {
|
|
|
|
|
@@ -193,10 +185,14 @@ struct dw_pcie_ep {
|
|
|
|
|
size_t page_size;
|
|
|
|
|
u8 bar_to_atu[6];
|
|
|
|
|
phys_addr_t *outbound_addr;
|
|
|
|
|
- unsigned long ib_window_map;
|
|
|
|
|
- unsigned long ob_window_map;
|
|
|
|
|
+ unsigned long *ib_window_map;
|
|
|
|
|
+ unsigned long *ob_window_map;
|
|
|
|
|
@@ -201,6 +193,10 @@ struct dw_pcie_ep {
|
|
|
|
|
unsigned long *ob_window_map;
|
|
|
|
|
u32 num_ib_windows;
|
|
|
|
|
u32 num_ob_windows;
|
|
|
|
|
+ void __iomem *msi_mem;
|
|
|
|
|
+ phys_addr_t msi_mem_phys;
|
|
|
|
|
+ u8 msi_cap; /* MSI capability offset */
|
|
|
|
|
+ u8 msix_cap; /* MSI-X capability offset */
|
|
|
|
|
+ void __iomem *msi_mem;
|
|
|
|
|
+ phys_addr_t msi_mem_phys;
|
|
|
|
|
+ u8 msi_cap; /* MSI capability offset */
|
|
|
|
|
+ u8 msix_cap; /* MSI-X capability offset */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct dw_pcie_ops {
|
|
|
|
|
@@ -335,6 +331,12 @@ static inline int dw_pcie_host_init(stru
|
|
|
|
|
@@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru
|
|
|
|
|
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
|
|
|
|
|
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
|
|
|
|
|
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
|
|
|
|
|
@ -1925,7 +1847,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
|
|
|
#else
|
|
|
|
|
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
|
|
|
|
|
{
|
|
|
|
|
@@ -348,5 +350,26 @@ static inline int dw_pcie_ep_init(struct
|
|
|
|
|
@@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct
|
|
|
|
|
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
Koen Vandeputte
5 years ago