kernel: backport SSB/BCMA changes in preparation for a compat-wireless update
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 36367v19.07.3_mercusys_ac12_duma
Felix Fietkau
11 years ago
parent
f03960723a
commit
f58dcb59c6
@ -0,0 +1,126 @@
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--- a/drivers/net/wireless/b43/phy_n.c
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+++ b/drivers/net/wireless/b43/phy_n.c
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@@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
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#endif
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#ifdef CONFIG_B43_SSB
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case B43_BUS_SSB:
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- /* FIXME */
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+ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
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+ avoid);
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break;
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#endif
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}
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
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return 0;
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}
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}
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+
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+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
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+{
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+ u32 pmu_ctl = 0;
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+
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+ switch (cc->dev->bus->chip_id) {
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+ case 0x4322:
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
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+ if (spuravoid == 1)
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
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+ else
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
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+ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
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+ break;
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+ case 43222:
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+ /* TODO: BCM43222 requires updating PLLs too */
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+ return;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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+ cc->dev->bus->chip_id);
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+ return;
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+ }
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+
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+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
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+}
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+EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
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return (s8)gain;
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}
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+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
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+{
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+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
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+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
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+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
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+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
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+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
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+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
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+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
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+ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
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+ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
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+ SSB_SPROM2_MAXP_A_LO_SHIFT);
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+}
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+
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static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
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SSB_SPROM1_ITSSI_A_SHIFT);
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SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
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SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
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- if (out->revision >= 2)
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- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+
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SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
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SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
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@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
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out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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SSB_SPROM1_AGAIN_A,
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SSB_SPROM1_AGAIN_A_SHIFT);
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+ if (out->revision >= 2)
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+ sprom_extract_r23(out, in);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -219,6 +219,7 @@
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#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
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#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
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#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
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+#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
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#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
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#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
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#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
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@@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
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void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
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enum ssb_pmu_ldo_volt_id id, u32 voltage);
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void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
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+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
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#endif /* LINUX_SSB_CHIPCO_H_ */
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -289,11 +289,11 @@
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#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
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-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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+#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
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+#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
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+#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
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#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM4_AGAIN0_SHIFT 0
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@ -0,0 +1,140 @@
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
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return value;
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}
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-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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+u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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{
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_get_alp_clock(cc);
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return 20000000;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
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static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
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{
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@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
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return res;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
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return res;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
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/*
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* If the bit is set to 0, chipcommon controlls this GPIO,
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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+ case BCMA_CHIP_ID_BCM4313:
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+ case BCMA_CHIP_ID_BCM43224:
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+ case BCMA_CHIP_ID_BCM43225:
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+ case BCMA_CHIP_ID_BCM43227:
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+ case BCMA_CHIP_ID_BCM43228:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43421:
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+ case BCMA_CHIP_ID_BCM43428:
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+ case BCMA_CHIP_ID_BCM43431:
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case BCMA_CHIP_ID_BCM4716:
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- case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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- case BCMA_CHIP_ID_BCM4313:
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- case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM4749:
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+ case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM53572:
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+ case BCMA_CHIP_ID_BCM6362:
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/* always 20Mhz */
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return 20000 * 1000;
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- case BCMA_CHIP_ID_BCM5356:
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case BCMA_CHIP_ID_BCM4706:
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+ case BCMA_CHIP_ID_BCM5356:
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/* always 25Mhz */
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return 25000 * 1000;
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+ case BCMA_CHIP_ID_BCM43460:
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+ case BCMA_CHIP_ID_BCM4352:
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+ case BCMA_CHIP_ID_BCM4360:
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+ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
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+ return 40000 * 1000;
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+ else
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+ return 20000 * 1000;
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default:
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bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM4331:
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@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM43224:
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@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM4716:
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@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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0x88888815);
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}
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- tmp = 3 << 9;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
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break;
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case BCMA_CHIP_ID_BCM43227:
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@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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default:
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bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -104,6 +104,7 @@
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#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
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#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
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#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
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+#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
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#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
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#define BCMA_CC_JCMD_START 0x80000000
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#define BCMA_CC_JCMD_BUSY 0x80000000
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@@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
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extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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+extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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+
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
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