brcm47xx: merge cpu cache workaround patches into one, ensure they get compiled out on mips74k
Signed-off-by: Felix Fietkau <nbd@nbd.name>v19.07.3_mercusys_ac12_duma
Felix Fietkau
8 years ago
parent
1cd7ff3e96
commit
f12f77b477
@ -1,138 +0,0 @@
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -28,10 +28,28 @@ extern void (*r4k_blast_icache)(void);
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#ifdef CONFIG_BCM47XX
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#include <asm/paccess.h>
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#include <linux/ssb/ssb.h>
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-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
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+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
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+
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+static inline unsigned long bcm4710_dummy_rreg(void)
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+{
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+ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
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+}
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+
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+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
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+
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+static inline unsigned long bcm4710_fill_tlb(void *addr)
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+{
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+ return *(unsigned long *)addr;
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+}
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+
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+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
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+
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+static inline void bcm4710_protected_fill_tlb(void *addr)
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+{
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+ unsigned long x;
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+ get_dbe(x, (unsigned long *)addr);;
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+}
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-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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#else
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#define BCM4710_DUMMY_RREG()
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -943,6 +943,9 @@ build_get_pgde32(u32 **p, unsigned int t
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uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
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uasm_i_addu(p, ptr, tmp, ptr);
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#else
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+#endif
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UASM_i_LA_mostly(p, ptr, pgdc);
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#endif
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uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
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@@ -1281,12 +1284,12 @@ static void build_r4000_tlb_refill_handl
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/* No need for uasm_i_nop */
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}
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-#ifdef CONFIG_BCM47XX
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- uasm_i_nop(&p);
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-#endif
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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+# ifdef CONFIG_BCM47XX
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+ uasm_i_nop(&p);
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+# endif
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build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
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#endif
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@@ -1298,6 +1301,9 @@ static void build_r4000_tlb_refill_handl
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build_update_entries(&p, K0, K1);
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build_tlb_write_entry(&p, &l, &r, tlb_random);
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uasm_l_leave(&l, p);
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(&p);
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+#endif
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uasm_i_eret(&p); /* return from trap */
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}
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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@@ -1871,12 +1877,12 @@ build_r4000_tlbchange_handler_head(u32 *
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{
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struct work_registers wr = build_get_work_registers(p);
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-#ifdef CONFIG_BCM47XX
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- uasm_i_nop(p);
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-#endif
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#ifdef CONFIG_64BIT
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build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
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#else
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+# ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+# endif
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build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
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#endif
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@@ -1923,6 +1929,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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build_tlb_write_entry(p, l, r, tlb_indexed);
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uasm_l_leave(l, *p);
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build_restore_work_registers(p);
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+#endif
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uasm_i_eret(p); /* return from trap */
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#ifdef CONFIG_64BIT
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--- a/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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@@ -21,6 +21,19 @@
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#include <asm/war.h>
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#include <asm/thread_info.h>
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+#ifdef CONFIG_BCM47XX
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+# ifdef eret
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+# undef eret
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+# endif
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+# define eret \
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+ .set push; \
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+ .set noreorder; \
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+ nop; \
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+ nop; \
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+ eret; \
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+ .set pop;
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+#endif
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+
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__INIT
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/*
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@@ -34,7 +47,6 @@ NESTED(except_vec3_generic, 0, sp)
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.set noat
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#ifdef CONFIG_BCM47XX
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nop
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- nop
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#endif
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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@@ -59,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
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.set push
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.set arch=r4000
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.set noat
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+#ifdef CONFIG_BCM47XX
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+ nop
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+#endif
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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