ar71xx: add initial support for the Qualcomm Atheros AP136 board
SVN-Revision: 32607v19.07.3_mercusys_ac12_duma
Gabor Juhos
12 years ago
parent
d1b237b335
commit
f0cda65bb6
@ -0,0 +1,213 @@
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From a034da3e4d4960266a94d15c811d5f4529fdff44 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 24 Jun 2012 13:52:23 +0200
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Subject: [PATCH 27/34] MIPS: ath79: add support for the Qualcomm Atheros AP136 board
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/Kconfig | 12 +++
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arch/mips/ath79/Makefile | 1 +
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arch/mips/ath79/mach-ap136.c | 155 ++++++++++++++++++++++++++++++++++++++++++
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arch/mips/ath79/machtypes.h | 1 +
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4 files changed, 169 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/ath79/mach-ap136.c
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
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Say 'Y' here if you want your kernel to support the
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Atheros AP121 reference board.
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+config ATH79_MACH_AP136
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+ bool "Atheros AP136 reference board"
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+ select SOC_QCA955X
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_SPI
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+ help
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+ Say 'Y' here if you want your kernel to support the
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+ Atheros AP136 reference board.
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+
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config ATH79_MACH_AP81
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bool "Atheros AP81 reference board"
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select SOC_AR913X
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--- a/arch/mips/ath79/Makefile
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+++ b/arch/mips/ath79/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma
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# Machines
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#
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obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
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+obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
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obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
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obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
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obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
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--- /dev/null
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+++ b/arch/mips/ath79/mach-ap136.c
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@@ -0,0 +1,155 @@
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+/*
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+ * Qualcomm Atheros AP136 reference board support
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+ *
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+ * Copyright (c) 2012 Qualcomm Atheros
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+ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for any
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+ * purpose with or without fee is hereby granted, provided that the above
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+ * copyright notice and this permission notice appear in all copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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+ *
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+ */
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+
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+#include <linux/pci.h>
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+#include <linux/ath9k_platform.h>
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+
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+#include "machtypes.h"
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+#include "dev-gpio-buttons.h"
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+#include "dev-leds-gpio.h"
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+#include "dev-spi.h"
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+#include "dev-usb.h"
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+#include "dev-wmac.h"
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+#include "pci.h"
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+
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+#define AP136_GPIO_LED_STATUS_RED 14
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+#define AP136_GPIO_LED_STATUS_GREEN 19
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+#define AP136_GPIO_LED_USB 4
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+#define AP136_GPIO_LED_WLAN_2G 13
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+#define AP136_GPIO_LED_WLAN_5G 12
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+#define AP136_GPIO_LED_WPS_RED 15
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+#define AP136_GPIO_LED_WPS_GREEN 20
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+
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+#define AP136_GPIO_BTN_WPS 16
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+#define AP136_GPIO_BTN_RFKILL 21
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+
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+#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
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+#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
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+
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+#define AP136_WMAC_CALDATA_OFFSET 0x1000
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+#define AP136_PCIE_CALDATA_OFFSET 0x5000
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+
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+static struct gpio_led ap136_leds_gpio[] __initdata = {
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+ {
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+ .name = "ap136:green:status",
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+ .gpio = AP136_GPIO_LED_STATUS_GREEN,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "ap136:red:status",
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+ .gpio = AP136_GPIO_LED_STATUS_RED,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "ap136:green:wps",
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+ .gpio = AP136_GPIO_LED_WPS_GREEN,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "ap136:red:wps",
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+ .gpio = AP136_GPIO_LED_WPS_RED,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "ap136:red:wlan-2g",
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+ .gpio = AP136_GPIO_LED_WLAN_2G,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "ap136:red:usb",
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+ .gpio = AP136_GPIO_LED_USB,
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+ .active_low = 1,
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+ }
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+};
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+
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+static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
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+ {
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+ .desc = "WPS button",
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+ .type = EV_KEY,
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+ .code = KEY_WPS_BUTTON,
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+ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
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+ .gpio = AP136_GPIO_BTN_WPS,
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+ .active_low = 1,
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+ },
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+ {
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+ .desc = "RFKILL button",
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+ .type = EV_KEY,
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+ .code = KEY_RFKILL,
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+ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
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+ .gpio = AP136_GPIO_BTN_RFKILL,
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+ .active_low = 1,
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+ },
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+};
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+
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+static struct spi_board_info ap136_spi_info[] = {
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+ {
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+ .bus_num = 0,
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+ .chip_select = 0,
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+ .max_speed_hz = 25000000,
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+ .modalias = "mx25l6405d",
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+ }
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+};
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+
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+static struct ath79_spi_platform_data ap136_spi_data = {
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+ .bus_num = 0,
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+ .num_chipselect = 1,
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+};
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+
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+#ifdef CONFIG_PCI
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+static struct ath9k_platform_data ap136_ath9k_data;
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+
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+static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+{
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+ if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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+ dev->dev.platform_data = &ap136_ath9k_data;
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+
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+ return 0;
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+}
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+
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+static void __init ap136_pci_init(u8 *eeprom)
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+{
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+ memcpy(ap136_ath9k_data.eeprom_data, eeprom,
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+ sizeof(ap136_ath9k_data.eeprom_data));
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+
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+ ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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+ ath79_register_pci();
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+}
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+#else
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+static inline void ap136_pci_init(void) {}
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+#endif /* CONFIG_PCI */
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+
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+static void __init ap136_setup(void)
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+{
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+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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+
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+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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+ ap136_leds_gpio);
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+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
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+ ARRAY_SIZE(ap136_gpio_keys),
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+ ap136_gpio_keys);
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+ ath79_register_spi(&ap136_spi_data, ap136_spi_info,
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+ ARRAY_SIZE(ap136_spi_info));
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+ ath79_register_usb();
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
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+ ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
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+}
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+
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+MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
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+ ap136_setup);
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--- a/arch/mips/ath79/machtypes.h
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+++ b/arch/mips/ath79/machtypes.h
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@@ -17,6 +17,7 @@
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enum ath79_mach_type {
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ATH79_MACH_GENERIC = 0,
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ATH79_MACH_AP121, /* Atheros AP121 reference board */
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+ ATH79_MACH_AP136, /* Atheros AP136 reference board */
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ATH79_MACH_AP81, /* Atheros AP81 reference board */
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ATH79_MACH_DB120, /* Atheros DB120 reference board */
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ATH79_MACH_PB44, /* Atheros PB44 reference board */
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@ -0,0 +1,175 @@
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--- a/arch/mips/ath79/mach-ap136.c
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+++ b/arch/mips/ath79/mach-ap136.c
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@@ -1,5 +1,5 @@
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/*
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- * Qualcomm Atheros AP136 reference board support
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+ * Atheros AP136 reference board support
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*
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* Copyright (c) 2012 Qualcomm Atheros
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* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
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@@ -18,23 +18,27 @@
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*
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*/
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-#include <linux/pci.h>
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-#include <linux/ath9k_platform.h>
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+#include <linux/platform_device.h>
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+#include <linux/ar8216_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#include "common.h"
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+#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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+#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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-#include "dev-spi.h"
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+#include "dev-m25p80.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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-#include "pci.h"
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+#include "machtypes.h"
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-#define AP136_GPIO_LED_STATUS_RED 14
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-#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_USB 4
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-#define AP136_GPIO_LED_WLAN_2G 13
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#define AP136_GPIO_LED_WLAN_5G 12
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+#define AP136_GPIO_LED_WLAN_2G 13
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+#define AP136_GPIO_LED_STATUS_RED 14
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#define AP136_GPIO_LED_WPS_RED 15
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+#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_WPS_GREEN 20
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#define AP136_GPIO_BTN_WPS 16
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@@ -43,8 +47,10 @@
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#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
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#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
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-#define AP136_WMAC_CALDATA_OFFSET 0x1000
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-#define AP136_PCIE_CALDATA_OFFSET 0x5000
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+#define AP136_MAC0_OFFSET 0
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+#define AP136_MAC1_OFFSET 6
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+#define AP136_WMAC_CALDATA_OFFSET 0x1000
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+#define AP136_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led ap136_leds_gpio[] __initdata = {
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{
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@@ -98,63 +104,82 @@ static struct gpio_keys_button ap136_gpi
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},
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};
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-static struct ath79_spi_controller_data ap136_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
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+ .mode = AR8327_PAD_MAC_RGMII,
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+ .txclk_delay_en = true,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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-static struct spi_board_info ap136_spi_info[] = {
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- {
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "mx25l6405d",
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- .controller_data = &ap136_spi0_data,
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+static struct ar8327_platform_data ap136_ar8327_data = {
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+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
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+ .cpuport_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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}
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};
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-static struct ath79_spi_platform_data ap136_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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+static struct mdio_board_info ap136_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &ap136_ar8327_data,
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+ },
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data ap136_ath9k_data;
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-
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+static void __init ap136_gmac_setup(void)
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{
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- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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- dev->dev.platform_data = &ap136_ath9k_data;
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+ void __iomem *base;
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+ u32 t;
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- return 0;
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-}
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+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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-static void __init ap136_pci_init(u8 *eeprom)
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-{
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- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
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- sizeof(ap136_ath9k_data.eeprom_data));
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+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
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+
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+ t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
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+ t |= QCA955X_ETH_CFG_RGMII_GMAC0;
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- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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- ath79_register_pci();
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+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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+
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+ iounmap(base);
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}
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-#else
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-static inline void ap136_pci_init(void) {}
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-#endif /* CONFIG_PCI */
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static void __init ap136_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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+ ath79_register_m25p80(NULL);
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+
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ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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ap136_leds_gpio);
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ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(ap136_gpio_keys),
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ap136_gpio_keys);
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- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
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- ARRAY_SIZE(ap136_spi_info));
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+
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ath79_register_usb();
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- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
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- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
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+
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+ ap136_gmac_setup();
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+
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+ ath79_register_mdio(0, 0x0);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
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+
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+ mdiobus_register_board_info(ap136_mdio0_info,
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+ ARRAY_SIZE(ap136_mdio0_info));
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+
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+ /* GMAC0 is connected to an AR8327 switch */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = BIT(0);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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+ ath79_eth0_pll_data.pll_1000 = 0x06000000;
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+
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+ ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
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