ar71xx: Kernel board definition for PowerCloud CR3000
Kernel part of support for PowerCloud CR3000. The CR3000 is
a 802.11n 2.4 GHz wireless router with 8MB flash, 64MB RAM,
a four port fast ethernet switch, and a fast ethernet wan port which
was sold by PowerCloud Systems as hardware for the Skydog
cloud-managed router service.
Signed-off-by: Daniel Dickinson <openwrt@daniel.thecshore.com>
SVN-Revision: 47939
v19.07.3_mercusys_ac12_duma
Felix Fietkau
9 years ago
parent
4cc541756d
commit
eef3b7acfb
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/*
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* PowerCloud Systems CR3000 support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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* Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2012-2013 PowerCloud Systems
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* Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/gpio.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define CR3000_GPIO_LED_WLAN_2G 13
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#define CR3000_GPIO_LED_POWER_AMBER 15
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#define CR3000_GPIO_LED_WAN 18
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#define CR3000_GPIO_LED_LAN1 19
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#define CR3000_GPIO_LED_LAN2 20
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#define CR3000_GPIO_LED_LAN3 21
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#define CR3000_GPIO_LED_LAN4 22
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#define CR3000_GPIO_BTN_WPS 16
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#define CR3000_GPIO_BTN_RESET 17
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#define CR3000_KEYS_POLL_INTERVAL 20 /* msecs */
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#define CR3000_KEYS_DEBOUNCE_INTERVAL (3 * CR3000_KEYS_POLL_INTERVAL)
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#define CR3000_MAC0_OFFSET 0
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#define CR3000_MAC1_OFFSET 6
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#define CR3000_WMAC_CALDATA_OFFSET 0x1000
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#define CR3000_WMAC_MAC_OFFSET 0x1002
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#define CR3000_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led cr3000_leds_gpio[] __initdata = {
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{
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.name = "pcs:amber:power",
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.gpio = CR3000_GPIO_LED_POWER_AMBER,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:wlan",
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.gpio = CR3000_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:wan",
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.gpio = CR3000_GPIO_LED_WAN,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:lan1",
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.gpio = CR3000_GPIO_LED_LAN1,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:lan2",
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.gpio = CR3000_GPIO_LED_LAN2,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:lan3",
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.gpio = CR3000_GPIO_LED_LAN3,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:lan4",
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.gpio = CR3000_GPIO_LED_LAN4,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button cr3000_gpio_keys[] __initdata = {
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{
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.desc = "WPS button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = CR3000_KEYS_DEBOUNCE_INTERVAL,
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.gpio = CR3000_GPIO_BTN_WPS,
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.active_low = 1,
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},
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = CR3000_KEYS_DEBOUNCE_INTERVAL,
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.gpio = CR3000_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static void __init cr3000_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(cr3000_leds_gpio),
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cr3000_leds_gpio);
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ath79_register_gpio_keys_polled(-1, CR3000_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(cr3000_gpio_keys),
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cr3000_gpio_keys);
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/* WLAN 2GHz onboard */
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ath79_register_wmac(art + CR3000_WMAC_CALDATA_OFFSET, art + CR3000_WMAC_MAC_OFFSET);
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ath79_register_mdio(1, 0x0);
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ath79_register_mdio(0, 0x0);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
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/* Lan 4-port switch attached to GMAC1 internal switch */
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ath79_init_mac(ath79_eth1_data.mac_addr, art + CR3000_MAC0_OFFSET, 0);
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_register_eth(1);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + CR3000_MAC1_OFFSET, 0);
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/* WAN Fast Ethernet interface attached to GMAC0 */
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ath79_switch_data.phy4_mii_en = 1;
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ath79_switch_data.phy_poll_mask = BIT(0);
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_CR3000, "CR3000", "PowerCloud CR3000",
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cr3000_setup);
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