ath79: add new ar934x spi driver
A new shift mode was introduced since ar934x which has a way better performance than current bitbang driver and can handle higher spi clock properly. This commit adds a new driver to make use of this new feature. This new driver has chipselect properly configured and we don't need cs-gpios hack in dts anymore. Remove them. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>master
Chuanhong Guo
4 years ago
parent
aca274091a
commit
ebf0d8dade
@ -0,0 +1,61 @@
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From 7945f929f1a77a1c8887a97ca07f87626858ff42 Mon Sep 17 00:00:00 2001
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From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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Date: Wed, 20 Feb 2019 11:12:39 +0000
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Subject: [PATCH] drivers: provide devm_platform_ioremap_resource()
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There are currently 1200+ instances of using platform_get_resource()
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and devm_ioremap_resource() together in the kernel tree.
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This patch wraps these two calls in a single helper. Thanks to that
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we don't have to declare a local variable for struct resource * and can
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omit the redundant argument for resource type. We also have one
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function call less.
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Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/base/platform.c | 18 ++++++++++++++++++
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include/linux/platform_device.h | 3 +++
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2 files changed, 21 insertions(+)
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--- a/drivers/base/platform.c
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+++ b/drivers/base/platform.c
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@@ -80,6 +80,24 @@ struct resource *platform_get_resource(s
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EXPORT_SYMBOL_GPL(platform_get_resource);
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/**
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+ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
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+ * device
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+ *
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+ * @pdev: platform device to use both for memory resource lookup as well as
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+ * resource managemend
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+ * @index: resource index
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+ */
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+void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
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+ unsigned int index)
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+{
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+ struct resource *res;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
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+ return devm_ioremap_resource(&pdev->dev, res);
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+}
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+EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
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+
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+/**
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* platform_get_irq - get an IRQ for a device
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* @dev: platform device
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* @num: IRQ number index
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--- a/include/linux/platform_device.h
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+++ b/include/linux/platform_device.h
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@@ -51,6 +51,9 @@ extern struct device platform_bus;
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extern void arch_setup_pdev_archdata(struct platform_device *);
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extern struct resource *platform_get_resource(struct platform_device *,
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unsigned int, unsigned int);
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+extern void __iomem *
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+devm_platform_ioremap_resource(struct platform_device *pdev,
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+ unsigned int index);
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extern int platform_get_irq(struct platform_device *, unsigned int);
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extern int platform_irq_count(struct platform_device *);
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extern struct resource *platform_get_resource_byname(struct platform_device *,
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@ -0,0 +1,277 @@
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From b518f18f89dbd49fe9403a8c92230f1af59219bc Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Wed, 5 Feb 2020 18:25:37 +0800
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Subject: [PATCH 1/2] spi: add driver for ar934x spi controller
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This patch adds driver for SPI controller found in Qualcomm Atheros
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AR934x/QCA95xx SoCs.
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This controller is a superset of the already supported qca,ar7100-spi.
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Besides the bit-bang mode in spi-ath79.c, this new controller added
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a new "shift register" mode, allowing faster spi operations.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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---
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drivers/spi/Kconfig | 7 ++
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-ar934x.c | 229 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 237 insertions(+)
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create mode 100644 drivers/spi/spi-ar934x.c
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -61,6 +61,13 @@ config SPI_ALTERA
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help
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This is the driver for the Altera SPI Controller.
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+config SPI_AR934X
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+ tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
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+ depends on ATH79 || COMPILE_TEST
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+ help
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+ This enables support for the SPI controller present on the
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+ Qualcomm Atheros AR934X/QCA95XX SoCs.
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+
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config SPI_ATH79
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tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
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depends on ATH79 && GPIOLIB
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-
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# SPI master controller drivers (bus)
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obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
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+obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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--- /dev/null
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+++ b/drivers/spi/spi-ar934x.c
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@@ -0,0 +1,229 @@
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+// SPDX-License-Identifier: GPL-2.0
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+//
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+// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
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+//
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+// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
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+//
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+// Based on spi-mt7621.c:
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+// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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+// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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+// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
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+
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+#include <linux/clk.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_device.h>
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+#include <linux/spi/spi.h>
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+
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+#define DRIVER_NAME "spi-ar934x"
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+
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+#define AR934X_SPI_REG_FS 0x00
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+#define AR934X_SPI_ENABLE BIT(0)
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+
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+#define AR934X_SPI_REG_CTRL 0x04
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+#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
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+
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+#define AR934X_SPI_DATAOUT 0x10
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+
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+#define AR934X_SPI_REG_SHIFT_CTRL 0x14
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+#define AR934X_SPI_SHIFT_EN BIT(31)
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+#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
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+#define AR934X_SPI_SHIFT_TERM 26
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+#define AR934X_SPI_SHIFT_VAL(cs, term, count) \
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+ (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \
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+ (term) << AR934X_SPI_SHIFT_TERM | (count))
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+
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+#define AR934X_SPI_DATAIN 0x18
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+
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+struct ar934x_spi {
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+ struct spi_controller *ctlr;
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+ void __iomem *base;
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+ struct clk *clk;
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+ unsigned int clk_freq;
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+};
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+
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+static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
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+{
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+ int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
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+
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+ if (div < 0)
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+ return 0;
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+ else if (div > AR934X_SPI_CLK_MASK)
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+ return -EINVAL;
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+ else
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+ return div;
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+}
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+
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+static int ar934x_spi_setup(struct spi_device *spi)
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+{
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+ struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
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+
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+ if ((spi->max_speed_hz == 0) ||
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+ (spi->max_speed_hz > (sp->clk_freq / 2))) {
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+ spi->max_speed_hz = sp->clk_freq / 2;
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+ } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
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+ dev_err(&spi->dev, "spi clock is too low\n");
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int ar934x_spi_transfer_one_message(struct spi_controller *master,
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+ struct spi_message *m)
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+{
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+ struct ar934x_spi *sp = spi_controller_get_devdata(master);
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+ struct spi_transfer *t = NULL;
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+ struct spi_device *spi = m->spi;
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+ unsigned long trx_done, trx_cur;
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+ int stat = 0;
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+ u8 term = 0;
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+ int div, i;
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+ u32 reg;
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+ const u8 *tx_buf;
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+ u8 *buf;
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+
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+ m->actual_length = 0;
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ if (t->speed_hz)
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+ div = ar934x_spi_clk_div(sp, t->speed_hz);
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+ else
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+ div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
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+ if (div < 0) {
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+ stat = -EIO;
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+ goto msg_done;
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+ }
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+
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+ reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
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+ reg &= ~AR934X_SPI_CLK_MASK;
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+ reg |= div;
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+ iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
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+ iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
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+
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+ for (trx_done = 0; trx_done < t->len; trx_done += 4) {
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+ trx_cur = t->len - trx_done;
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+ if (trx_cur > 4)
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+ trx_cur = 4;
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+ else if (list_is_last(&t->transfer_list, &m->transfers))
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+ term = 1;
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+
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+ if (t->tx_buf) {
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+ tx_buf = t->tx_buf + trx_done;
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+ reg = tx_buf[0];
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+ for (i = 1; i < trx_cur; i++)
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+ reg = reg << 8 | tx_buf[i];
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+ iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
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+ }
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+
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+ reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
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+ trx_cur * 8);
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+ iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
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+ stat = readl_poll_timeout(
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+ sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
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+ !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
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+ if (stat < 0)
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+ goto msg_done;
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+
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+ if (t->rx_buf) {
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+ reg = ioread32(sp->base + AR934X_SPI_DATAIN);
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+ buf = t->rx_buf + trx_done;
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+ for (i = 0; i < trx_cur; i++) {
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+ buf[trx_cur - i - 1] = reg & 0xff;
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+ reg >>= 8;
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+ }
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+ }
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+ }
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+ m->actual_length += t->len;
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+ }
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+
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+msg_done:
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+ m->status = stat;
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+ spi_finalize_current_message(master);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id ar934x_spi_match[] = {
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+ { .compatible = "qca,ar934x-spi" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ar934x_spi_match);
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+
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+static int ar934x_spi_probe(struct platform_device *pdev)
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+{
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+ struct spi_controller *ctlr;
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+ struct ar934x_spi *sp;
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+ void __iomem *base;
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+ struct clk *clk;
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+ int ret;
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+
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+ base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ clk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(clk)) {
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+ dev_err(&pdev->dev, "failed to get clock\n");
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+ return PTR_ERR(clk);
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+ }
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+
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+ ret = clk_prepare_enable(clk);
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+ if (ret)
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+ return ret;
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+
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+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
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+ if (!ctlr) {
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+ dev_info(&pdev->dev, "failed to allocate spi controller\n");
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+ return -ENOMEM;
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+ }
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+
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+ iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
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+
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+ ctlr->mode_bits = SPI_LSB_FIRST;
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+ ctlr->setup = ar934x_spi_setup;
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+ ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
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+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
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+ ctlr->dev.of_node = pdev->dev.of_node;
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+ ctlr->num_chipselect = 3;
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+
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+ dev_set_drvdata(&pdev->dev, ctlr);
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+
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+ sp = spi_controller_get_devdata(ctlr);
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+ sp->base = base;
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+ sp->clk = clk;
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+ sp->clk_freq = clk_get_rate(clk);
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+ sp->ctlr = ctlr;
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+
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+ return devm_spi_register_controller(&pdev->dev, ctlr);
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+}
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+
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+static int ar934x_spi_remove(struct platform_device *pdev)
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+{
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+ struct spi_controller *ctlr;
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+ struct ar934x_spi *sp;
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+
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+ ctlr = dev_get_drvdata(&pdev->dev);
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+ sp = spi_controller_get_devdata(ctlr);
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+
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+ clk_disable_unprepare(sp->clk);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver ar934x_spi_driver = {
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+ .driver = {
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+ .name = DRIVER_NAME,
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+ .of_match_table = ar934x_spi_match,
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+ },
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+ .probe = ar934x_spi_probe,
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+ .remove = ar934x_spi_remove,
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+};
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+
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+module_platform_driver(ar934x_spi_driver);
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+
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+MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
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+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
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+MODULE_LICENSE("GPL v2");
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+MODULE_ALIAS("platform:" DRIVER_NAME);
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